x86/msr: AMD MSR_SPEC_CTRL infrastructure

Fill in VMCB accessors for spec_ctrl in svm_{get,set}_reg(), and CPUID checks
for all supported bits in guest_{rd,wr}msr().

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
This commit is contained in:
Andrew Cooper committed 2022-02-01 13:20:44 +00:00
1 parent 614cec7d79
commit 22b9add22b
2 files changed
+14 -3

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+9
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@@ -2471,10 +2471,14 @@ static bool svm_get_pending_event(struct vcpu *v, struct x86_event *info)
static uint64_t svm_get_reg(struct vcpu *v, unsigned int reg)
{
const struct vmcb_struct *vmcb = v->arch.hvm.svm.vmcb;
struct domain *d = v->domain;
switch ( reg )
{
case MSR_SPEC_CTRL:
return vmcb->spec_ctrl;
default:
printk(XENLOG_G_ERR "%s(%pv, 0x%08x) Bad register\n",
__func__, v, reg);
@@ -2485,10 +2489,15 @@ static uint64_t svm_get_reg(struct vcpu *v, unsigned int reg)
static void svm_set_reg(struct vcpu *v, unsigned int reg, uint64_t val)
{
struct vmcb_struct *vmcb = v->arch.hvm.svm.vmcb;
struct domain *d = v->domain;
switch ( reg )
{
case MSR_SPEC_CTRL:
vmcb->spec_ctrl = val;
break;
default:
printk(XENLOG_G_ERR "%s(%pv, 0x%08x, 0x%016"PRIx64") Bad register\n",
__func__, v, reg, val);
+5 -3
View File
@@ -265,7 +265,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
break;
case MSR_SPEC_CTRL:
if ( !cp->feat.ibrsb )
if ( !cp->feat.ibrsb && !cp->extd.ibrs )
goto gp_fault;
goto get_reg;
@@ -442,7 +442,8 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
*/
uint64_t msr_spec_ctrl_valid_bits(const struct cpuid_policy *cp)
{
bool ssbd = cp->feat.ssbd;
bool ssbd = cp->feat.ssbd || cp->extd.amd_ssbd;
bool psfd = cp->extd.psfd;
/*
* Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. ignored)
@@ -450,6 +451,7 @@ uint64_t msr_spec_ctrl_valid_bits(const struct cpuid_policy *cp)
*/
return (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
(ssbd ? SPEC_CTRL_SSBD : 0) |
(psfd ? SPEC_CTRL_PSFD : 0) |
0);
}
@@ -526,7 +528,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
break;
case MSR_SPEC_CTRL:
if ( !cp->feat.ibrsb ||
if ( (!cp->feat.ibrsb && !cp->extd.ibrs) ||
(val & ~msr_spec_ctrl_valid_bits(cp)) )
goto gp_fault;
goto set_reg;
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