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vt-d: fix IM bit mask and unmask of Fault Event Control Register
Bit 0:29 in Fault Event Control Register are 'Reserved and Preserved', software cannot write 0 to it unconditionally. Software must preserve the value read for writes. Signed-off-by: Quan Xu <quan.xu@intel.com> Acked-by: Yang Zhang <yang.z.zhang@intel.com> vt-d: fix IM bit unmask of Fault Event Control Register in init_vtd_hw() Bit 0:29 in Fault Event Control Register are 'Reserved and Preserved', software cannot write 0 to it unconditionally. Software must preserve the value read for writes. Suggested-by: Jan Beulich <jbeulich@suse.com> Signed-off-by: Quan Xu <quan.xu@intel.com> master commit:86f3ff9fc4master date: 2015-09-25 09:08:22 +0200 master commit:26b300bd72master date: 2015-09-25 18:03:04 +0200
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1 parent
964150bf9d
commit
2327dadbeb
1 file changed
+12
-3
@@ -992,10 +992,13 @@ static void dma_msi_unmask(struct irq_desc *desc)
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{
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struct iommu *iommu = desc->action->dev_id;
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unsigned long flags;
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u32 sts;
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/* unmask it */
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spin_lock_irqsave(&iommu->register_lock, flags);
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dmar_writel(iommu->reg, DMAR_FECTL_REG, 0);
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sts = dmar_readl(iommu->reg, DMAR_FECTL_REG);
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sts &= ~DMA_FECTL_IM;
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dmar_writel(iommu->reg, DMAR_FECTL_REG, sts);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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iommu->msi.msi_attrib.masked = 0;
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}
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@@ -1004,10 +1007,13 @@ static void dma_msi_mask(struct irq_desc *desc)
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{
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unsigned long flags;
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struct iommu *iommu = desc->action->dev_id;
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u32 sts;
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/* mask it */
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spin_lock_irqsave(&iommu->register_lock, flags);
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dmar_writel(iommu->reg, DMAR_FECTL_REG, DMA_FECTL_IM);
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sts = dmar_readl(iommu->reg, DMAR_FECTL_REG);
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sts |= DMA_FECTL_IM;
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dmar_writel(iommu->reg, DMAR_FECTL_REG, sts);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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iommu->msi.msi_attrib.masked = 1;
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}
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@@ -2055,6 +2061,7 @@ static int init_vtd_hw(void)
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struct iommu_flush *flush = NULL;
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int ret;
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unsigned long flags;
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u32 sts;
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/*
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* Basic VT-d HW init: set VT-d interrupt, clear VT-d faults.
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@@ -2068,7 +2075,9 @@ static int init_vtd_hw(void)
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clear_fault_bits(iommu);
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spin_lock_irqsave(&iommu->register_lock, flags);
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dmar_writel(iommu->reg, DMAR_FECTL_REG, 0);
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sts = dmar_readl(iommu->reg, DMAR_FECTL_REG);
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sts &= ~DMA_FECTL_IM;
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dmar_writel(iommu->reg, DMAR_FECTL_REG, sts);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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}
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