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x86: eliminate old-CPU support bits
Some pieces can be removed altogether, others are only of possible use in 32-bit builds. Signed-off-by: Jan Beulich <jbeulich@novell.com>
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Jan Beulich committed
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@@ -15,15 +15,8 @@
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#include "cpu.h"
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#define tsc_disable 0
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#define disable_pse 0
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static int cachesize_override __cpuinitdata = -1;
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size_param("cachesize", cachesize_override);
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static bool_t __cpuinitdata disable_x86_fxsr;
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boolean_param("nofxsr", disable_x86_fxsr);
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static bool_t __cpuinitdata disable_x86_serial_nr;
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boolean_param("noserialnumber", disable_x86_serial_nr);
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static bool_t __cpuinitdata use_xsave;
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boolean_param("xsave", use_xsave);
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@@ -191,28 +184,6 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
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}
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/* Standard macro to see if a specific flag is changeable */
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static inline int flag_is_changeable_p(unsigned long flag)
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{
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unsigned long f1, f2;
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asm("pushf\n\t"
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"pushf\n\t"
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"pop %0\n\t"
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"mov %0,%1\n\t"
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"xor %2,%0\n\t"
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"push %0\n\t"
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"popf\n\t"
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"pushf\n\t"
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"pop %0\n\t"
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"popf\n\t"
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: "=&r" (f1), "=&r" (f2)
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: "ir" (flag));
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return ((f1^f2) & flag) != 0;
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}
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/* Do minimum CPU detection early.
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Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
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The others are not touched to avoid unwanted side effects.
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@@ -302,6 +273,14 @@ void __cpuinit generic_identify(struct cpuinfo_x86 * c)
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#endif
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}
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#ifdef __i386__
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static bool_t __cpuinitdata disable_x86_fxsr;
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boolean_param("nofxsr", disable_x86_fxsr);
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static bool_t __cpuinitdata disable_x86_serial_nr;
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boolean_param("noserialnumber", disable_x86_serial_nr);
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static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
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{
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if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
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@@ -317,6 +296,7 @@ static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
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}
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}
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#endif
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/*
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* This does the hard work of actually picking apart the CPU stuff...
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@@ -376,26 +356,24 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
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if ( cpu_has_xsave )
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xsave_init();
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/* Disable the PN if appropriate */
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squash_the_stupid_serial_number(c);
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/*
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* The vendor-specific functions might have changed features. Now
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* we do "generic changes."
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*/
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/* TSC disabled? */
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if ( tsc_disable )
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clear_bit(X86_FEATURE_TSC, c->x86_capability);
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#ifdef __i386__
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/* Disable the PN if appropriate */
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squash_the_stupid_serial_number(c);
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/* FXSR disabled? */
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if (disable_x86_fxsr) {
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clear_bit(X86_FEATURE_FXSR, c->x86_capability);
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clear_bit(X86_FEATURE_XMM, c->x86_capability);
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if (!cpu_has_xsave) {
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clear_bit(X86_FEATURE_XMM, c->x86_capability);
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clear_bit(X86_FEATURE_AES, c->x86_capability);
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}
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}
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if (disable_pse)
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clear_bit(X86_FEATURE_PSE, c->x86_capability);
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#endif
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for (i = 0 ; i < NCAPINTS ; ++i)
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c->x86_capability[i] &= ~cleared_caps[i];
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@@ -101,6 +101,7 @@
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#define X86_FEATURE_X2APIC (4*32+21) /* Extended xAPIC */
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#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
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#define X86_FEATURE_TSC_DEADLINE (4*32+24) /* "tdt" TSC Deadline Timer */
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#define X86_FEATURE_AES (4*32+25) /* AES instructions */
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#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
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#define X86_FEATURE_OSXSAVE (4*32+27) /* OSXSAVE */
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#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
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