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x86emul: drop host_and_vcpu_must_have()

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With CPU policy dependency logic now properly in place and working, and
with us never enabling ISA bits in guest policies which the underlying
hardware doesn't support, the dual checks aren't needed anymore.

In turn, a number of cpu_has_* can then also go away, when their only user
was the emulator code.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
This commit is contained in:
Jan Beulich committed 2026-07-28 10:16:00 +02:00
1 parent 78607876a2
commit 25cf3956b2
6 files changed
+221 -292
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xen/arch/x86/include/asm/cpufeature.h
-51
View File
@@ -126,28 +126,18 @@ static inline bool boot_cpu_has(unsigned int feat)
#define cpu_has_pge 1
#define cpu_has_pse36 boot_cpu_has(X86_FEATURE_PSE36)
#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH)
#define cpu_has_mmx 1
#define cpu_has_htt boot_cpu_has(X86_FEATURE_HTT)
/* CPUID level 0x00000001.ecx */
#define cpu_has_sse3 boot_cpu_has(X86_FEATURE_SSE3)
#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ)
#define cpu_has_monitor boot_cpu_has(X86_FEATURE_MONITOR)
#define cpu_has_vmx boot_cpu_has(X86_FEATURE_VMX)
#define cpu_has_eist boot_cpu_has(X86_FEATURE_EIST)
#define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3)
#define cpu_has_fma boot_cpu_has(X86_FEATURE_FMA)
#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
#define cpu_has_pdcm boot_cpu_has(X86_FEATURE_PDCM)
#define cpu_has_pcid boot_cpu_has(X86_FEATURE_PCID)
#define cpu_has_sse4_1 boot_cpu_has(X86_FEATURE_SSE4_1)
#define cpu_has_sse4_2 boot_cpu_has(X86_FEATURE_SSE4_2)
#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
#define cpu_has_popcnt boot_cpu_has(X86_FEATURE_POPCNT)
#define cpu_has_aesni boot_cpu_has(X86_FEATURE_AESNI)
#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
#define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX)
#define cpu_has_f16c boot_cpu_has(X86_FEATURE_F16C)
#define cpu_has_rdrand boot_cpu_has(X86_FEATURE_RDRAND)
#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
@@ -156,17 +146,11 @@ static inline bool boot_cpu_has(unsigned int feat)
boot_cpu_has(X86_FEATURE_NX))
#define cpu_has_page1gb boot_cpu_has(X86_FEATURE_PAGE1GB)
#define cpu_has_rdtscp boot_cpu_has(X86_FEATURE_RDTSCP)
#define cpu_has_3dnow_ext boot_cpu_has(X86_FEATURE_3DNOWEXT)
#define cpu_has_3dnow boot_cpu_has(X86_FEATURE_3DNOW)
/* CPUID level 0x80000001.ecx */
#define cpu_has_cmp_legacy boot_cpu_has(X86_FEATURE_CMP_LEGACY)
#define cpu_has_svm boot_cpu_has(X86_FEATURE_SVM)
#define cpu_has_sse4a boot_cpu_has(X86_FEATURE_SSE4A)
#define cpu_has_xop boot_cpu_has(X86_FEATURE_XOP)
#define cpu_has_skinit boot_cpu_has(X86_FEATURE_SKINIT)
#define cpu_has_fma4 boot_cpu_has(X86_FEATURE_FMA4)
#define cpu_has_tbm boot_cpu_has(X86_FEATURE_TBM)
/* CPUID level 0x00000006.eax */
#define cpu_has_turbo_boost host_cpu_policy.basic.turbo_boost
@@ -190,43 +174,23 @@ static inline bool boot_cpu_has(unsigned int feat)
#define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES)
/* CPUID level 0x00000007:0.ebx */
#define cpu_has_bmi1 boot_cpu_has(X86_FEATURE_BMI1)
#define cpu_has_hle boot_cpu_has(X86_FEATURE_HLE)
#define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2)
#define cpu_has_smep boot_cpu_has(X86_FEATURE_SMEP)
#define cpu_has_bmi2 boot_cpu_has(X86_FEATURE_BMI2)
#define cpu_has_invpcid boot_cpu_has(X86_FEATURE_INVPCID)
#define cpu_has_rtm boot_cpu_has(X86_FEATURE_RTM)
#define cpu_has_pqe boot_cpu_has(X86_FEATURE_PQE)
#define cpu_has_fpu_sel (!boot_cpu_has(X86_FEATURE_NO_FPU_SEL))
#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX)
#define cpu_has_avx512f boot_cpu_has(X86_FEATURE_AVX512F)
#define cpu_has_avx512dq boot_cpu_has(X86_FEATURE_AVX512DQ)
#define cpu_has_rdseed boot_cpu_has(X86_FEATURE_RDSEED)
#define cpu_has_smap boot_cpu_has(X86_FEATURE_SMAP)
#define cpu_has_avx512_ifma boot_cpu_has(X86_FEATURE_AVX512_IFMA)
#define cpu_has_clflushopt boot_cpu_has(X86_FEATURE_CLFLUSHOPT)
#define cpu_has_clwb boot_cpu_has(X86_FEATURE_CLWB)
#define cpu_has_avx512cd boot_cpu_has(X86_FEATURE_AVX512CD)
#define cpu_has_proc_trace boot_cpu_has(X86_FEATURE_PROC_TRACE)
#define cpu_has_sha boot_cpu_has(X86_FEATURE_SHA)
#define cpu_has_avx512bw boot_cpu_has(X86_FEATURE_AVX512BW)
#define cpu_has_avx512vl boot_cpu_has(X86_FEATURE_AVX512VL)
/* CPUID level 0x00000007:0.ecx */
#define cpu_has_avx512_vbmi boot_cpu_has(X86_FEATURE_AVX512_VBMI)
#define cpu_has_pku boot_cpu_has(X86_FEATURE_PKU)
#define cpu_has_avx512_vbmi2 boot_cpu_has(X86_FEATURE_AVX512_VBMI2)
#define cpu_has_gfni boot_cpu_has(X86_FEATURE_GFNI)
#define cpu_has_vaes boot_cpu_has(X86_FEATURE_VAES)
#define cpu_has_vpclmulqdq boot_cpu_has(X86_FEATURE_VPCLMULQDQ)
#define cpu_has_avx512_vnni boot_cpu_has(X86_FEATURE_AVX512_VNNI)
#define cpu_has_avx512_bitalg boot_cpu_has(X86_FEATURE_AVX512_BITALG)
#define cpu_has_avx512_vpopcntdq boot_cpu_has(X86_FEATURE_AVX512_VPOPCNTDQ)
#define cpu_has_rdpid boot_cpu_has(X86_FEATURE_RDPID)
#define cpu_has_movdiri boot_cpu_has(X86_FEATURE_MOVDIRI)
#define cpu_has_movdir64b boot_cpu_has(X86_FEATURE_MOVDIR64B)
#define cpu_has_enqcmd boot_cpu_has(X86_FEATURE_ENQCMD)
#define cpu_has_pks boot_cpu_has(X86_FEATURE_PKS)
/* CPUID level 0x80000007.edx */
@@ -241,38 +205,23 @@ static inline bool boot_cpu_has(unsigned int feat)
#define cpu_has_auto_ibrs boot_cpu_has(X86_FEATURE_AUTO_IBRS)
/* CPUID level 0x00000007:0.edx */
#define cpu_has_avx512_vp2intersect boot_cpu_has(X86_FEATURE_AVX512_VP2INTERSECT)
#define cpu_has_srbds_ctrl boot_cpu_has(X86_FEATURE_SRBDS_CTRL)
#define cpu_has_md_clear boot_cpu_has(X86_FEATURE_MD_CLEAR)
#define cpu_has_rtm_always_abort boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)
#define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)
#define cpu_has_serialize boot_cpu_has(X86_FEATURE_SERIALIZE)
#define cpu_has_hybrid boot_cpu_has(X86_FEATURE_HYBRID)
#define cpu_has_avx512_fp16 boot_cpu_has(X86_FEATURE_AVX512_FP16)
#define cpu_has_arch_caps boot_cpu_has(X86_FEATURE_ARCH_CAPS)
/* CPUID level 0x00000007:1.eax */
#define cpu_has_sha512 boot_cpu_has(X86_FEATURE_SHA512)
#define cpu_has_sm3 boot_cpu_has(X86_FEATURE_SM3)
#define cpu_has_sm4 boot_cpu_has(X86_FEATURE_SM4)
#define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI)
#define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16)
#define cpu_has_cmpccxadd boot_cpu_has(X86_FEATURE_CMPCCXADD)
#define cpu_has_fred boot_cpu_has(X86_FEATURE_FRED)
#define cpu_has_lkgs boot_cpu_has(X86_FEATURE_LKGS)
#define cpu_has_nmi_src boot_cpu_has(X86_FEATURE_NMI_SRC)
#define cpu_has_avx_ifma boot_cpu_has(X86_FEATURE_AVX_IFMA)
/* CPUID level 0x80000021.eax */
#define cpu_has_lfence_dispatch boot_cpu_has(X86_FEATURE_LFENCE_DISPATCH)
#define cpu_has_verw_clear boot_cpu_has(X86_FEATURE_VERW_CLEAR)
#define cpu_has_nscb boot_cpu_has(X86_FEATURE_NSCB)
/* CPUID level 0x00000007:1.edx */
#define cpu_has_avx_vnni_int8 boot_cpu_has(X86_FEATURE_AVX_VNNI_INT8)
#define cpu_has_avx_ne_convert boot_cpu_has(X86_FEATURE_AVX_NE_CONVERT)
#define cpu_has_avx_vnni_int16 boot_cpu_has(X86_FEATURE_AVX_VNNI_INT16)
/* MSR_ARCH_CAPS */
#define cpu_has_rdcl_no boot_cpu_has(X86_FEATURE_RDCL_NO)
#define cpu_has_eibrs boot_cpu_has(X86_FEATURE_EIBRS)
xen/arch/x86/x86_emulate/0f01.c
+1 -1
View File
@@ -121,7 +121,7 @@ int x86emul_0f01(struct x86_emulate_state *s,
switch ( s->vex.pfx )
{
case vex_none: /* serialize */
host_and_vcpu_must_have(serialize);
vcpu_must_have(serialize);
asm volatile ( ".byte 0x0f, 0x01, 0xe8" ); /* Binutils >= 2.34, Clang >= 11 */
break;
case vex_f2: /* xsusldtrk */
xen/arch/x86/x86_emulate/0fc7.c
+3 -3
View File
@@ -33,7 +33,7 @@ int x86emul_0fc7(struct x86_emulate_state *s,
case 6: /* rdrand */
generate_exception_if(s->vex.pfx >= vex_f3, X86_EXC_UD);
host_and_vcpu_must_have(rdrand);
vcpu_must_have(rdrand);
*dst = s->ea;
switch ( s->op_bytes )
{
@@ -75,7 +75,7 @@ int x86emul_0fc7(struct x86_emulate_state *s,
}
generate_exception_if(s->vex.pfx >= vex_f3, X86_EXC_UD);
host_and_vcpu_must_have(rdseed);
vcpu_must_have(rdseed);
*dst = s->ea;
switch ( s->op_bytes )
{
@@ -112,7 +112,7 @@ int x86emul_0fc7(struct x86_emulate_state *s,
fail_if(!ops->cmpxchg);
if ( s->rex_prefix & REX_W )
{
host_and_vcpu_must_have(cx16);
vcpu_must_have(cx16);
generate_exception_if(!is_aligned(s->ea.mem.seg, s->ea.mem.off, 16,
ctxt, ops),
X86_EXC_GP, 0);
xen/arch/x86/x86_emulate/fpu.c
+12 -12
View File
@@ -96,13 +96,13 @@ int x86emul_fpu(struct x86_emulate_state *s,
unsigned long dummy;
case 0x9b: /* wait/fwait */
host_and_vcpu_must_have(fpu);
vcpu_must_have(fpu);
get_fpu(X86EMUL_FPU_wait);
emulate_fpu_insn_stub(b);
break;
case 0xd8: /* FPU 0xd8 */
host_and_vcpu_must_have(fpu);
vcpu_must_have(fpu);
get_fpu(X86EMUL_FPU_fpu);
switch ( s->modrm )
{
@@ -128,7 +128,7 @@ int x86emul_fpu(struct x86_emulate_state *s,
break;
case 0xd9: /* FPU 0xd9 */
host_and_vcpu_must_have(fpu);
vcpu_must_have(fpu);
get_fpu(X86EMUL_FPU_fpu);
switch ( s->modrm )
{
@@ -229,7 +229,7 @@ int x86emul_fpu(struct x86_emulate_state *s,
break;
case 0xda: /* FPU 0xda */
host_and_vcpu_must_have(fpu);
vcpu_must_have(fpu);
get_fpu(X86EMUL_FPU_fpu);
switch ( s->modrm )
{
@@ -250,7 +250,7 @@ int x86emul_fpu(struct x86_emulate_state *s,
break;
case 0xdb: /* FPU 0xdb */
host_and_vcpu_must_have(fpu);
vcpu_must_have(fpu);
get_fpu(X86EMUL_FPU_fpu);
switch ( s->modrm )
{
@@ -279,7 +279,7 @@ int x86emul_fpu(struct x86_emulate_state *s,
case 0: /* fild m32i */
goto fpu_memsrc32;
case 1: /* fisttp m32i */
host_and_vcpu_must_have(sse3);
vcpu_must_have(sse3);
/* fall through */
case 2: /* fist m32i */
case 3: /* fistp m32i */
@@ -308,7 +308,7 @@ int x86emul_fpu(struct x86_emulate_state *s,
break;
case 0xdc: /* FPU 0xdc */
host_and_vcpu_must_have(fpu);
vcpu_must_have(fpu);
get_fpu(X86EMUL_FPU_fpu);
switch ( s->modrm )
{
@@ -334,7 +334,7 @@ int x86emul_fpu(struct x86_emulate_state *s,
break;
case 0xdd: /* FPU 0xdd */
host_and_vcpu_must_have(fpu);
vcpu_must_have(fpu);
get_fpu(X86EMUL_FPU_fpu);
switch ( s->modrm )
{
@@ -353,7 +353,7 @@ int x86emul_fpu(struct x86_emulate_state *s,
case 0: /* fld m64fp */;
goto fpu_memsrc64;
case 1: /* fisttp m64i */
host_and_vcpu_must_have(sse3);
vcpu_must_have(sse3);
/* fall through */
case 2: /* fst m64fp */
case 3: /* fstp m64fp */
@@ -399,7 +399,7 @@ int x86emul_fpu(struct x86_emulate_state *s,
break;
case 0xde: /* FPU 0xde */
host_and_vcpu_must_have(fpu);
vcpu_must_have(fpu);
get_fpu(X86EMUL_FPU_fpu);
switch ( s->modrm )
{
@@ -421,7 +421,7 @@ int x86emul_fpu(struct x86_emulate_state *s,
break;
case 0xdf: /* FPU 0xdf */
host_and_vcpu_must_have(fpu);
vcpu_must_have(fpu);
get_fpu(X86EMUL_FPU_fpu);
switch ( s->modrm )
{
@@ -451,7 +451,7 @@ int x86emul_fpu(struct x86_emulate_state *s,
case 0: /* fild m16i */
goto fpu_memsrc16;
case 1: /* fisttp m16i */
host_and_vcpu_must_have(sse3);
vcpu_must_have(sse3);
/* fall through */
case 2: /* fist m16i */
case 3: /* fistp m16i */
xen/arch/x86/x86_emulate/private.h
-20
View File
@@ -620,26 +620,6 @@ amd_like(const struct x86_emulate_ctxt *ctxt)
#define vcpu_must_have(feat) \
generate_exception_if(!vcpu_has_##feat(), X86_EXC_UD)
#ifdef __XEN__
/*
* Note the difference between vcpu_must_have(<feature>) and
* host_and_vcpu_must_have(<feature>): The latter needs to be used when
* emulation code is using the same instruction class for carrying out
* the actual operation.
*/
# define host_and_vcpu_must_have(feat) ({ \
generate_exception_if(!cpu_has_##feat, X86_EXC_UD); \
vcpu_must_have(feat); \
})
#else
/*
* For the test harness both are fine to be used interchangeably, i.e.
* features known to always be available (e.g. SSE/SSE2) to (64-bit) Xen
* may be checked for by just vcpu_must_have().
*/
# define host_and_vcpu_must_have(feat) vcpu_must_have(feat)
#endif
/*
* Instruction emulation:
* Most instructions are emulated directly via a fragment of inline assembly
xen/arch/x86/x86_emulate/x86_emulate.c
+205 -205
View File
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