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xen/arm: smccc: Preserve argument types in v1.1 SMC
The SMCCC v1.1 inline helper currently forces a1-a4 into
unsigned long and uses in/out constraints for r0-r3. In
contrast, a5-a7 are passed with their original types via
read-only constraints. On arm64 this means a 32-bit signed
value in a1-a4 is converted to a 64-bit unsigned value, while
the same value in a5-a7 keeps its signed 32-bit form. For
example, a negative int in a2 is widened to unsigned long, but
a negative int in a5 is passed as a 32-bit signed value, so the
SMC sees different encodings depending on argument position.
Switch the helper to use typed input registers arg0-arg7
derived from the call arguments (keeping a0 cast to u32) and
separate output registers r0-r3. This preserves argument types
consistently across all positions. Argument evaluation order
is unchanged, so we do not reintroduce the issue fixed in
"e00dc325bd9e" ("xen/arm: smccc-1.1: Handle function result as
parameters").
This also aligns Xen's SMCCC parameter handling with Linux's type-
preserving behavior (same externally visible argument handling,
independent implementation) to avoid surprising differences
between a1-a4 and a5-a7.
Current callers (PSCI, SCMI, platform SMC pass-through, OP-TEE,
and exynos5) pass unsigned values; exynos5 passes an int CPU id
which should always be > 0.
Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
This commit is contained in:
Bertrand Marquis authored and Michal Orzel committed
1 parent
b5174863a4
commit
28af7ed910
1 file changed
+27
-42
@@ -99,87 +99,68 @@ struct arm_smccc_res {
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#define __count_args(...) \
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___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0)
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#define __constraint_write_0 \
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"+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3)
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#define __constraint_write_1 \
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"+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3)
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#define __constraint_write_2 \
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"+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3)
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#define __constraint_write_3 \
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"+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3)
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#define __constraint_write_4 __constraint_write_3
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#define __constraint_write_5 __constraint_write_4
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#define __constraint_write_6 __constraint_write_5
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#define __constraint_write_7 __constraint_write_6
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#define __constraint_read_0
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#define __constraint_read_1
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#define __constraint_read_2
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#define __constraint_read_3
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#define __constraint_read_4 "r" (r4)
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#define __constraint_read_5 __constraint_read_4, "r" (r5)
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#define __constraint_read_6 __constraint_read_5, "r" (r6)
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#define __constraint_read_7 __constraint_read_6, "r" (r7)
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#define __constraint_read_0 "r" (arg0)
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#define __constraint_read_1 __constraint_read_0, "r" (arg1)
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#define __constraint_read_2 __constraint_read_1, "r" (arg2)
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#define __constraint_read_3 __constraint_read_2, "r" (arg3)
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#define __constraint_read_4 __constraint_read_3, "r" (arg4)
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#define __constraint_read_5 __constraint_read_4, "r" (arg5)
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#define __constraint_read_6 __constraint_read_5, "r" (arg6)
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#define __constraint_read_7 __constraint_read_6, "r" (arg7)
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#define __declare_arg_0(a0, res) \
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struct arm_smccc_res *___res = (res); \
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register unsigned long r0 ASM_REG(0) = (uint32_t)(a0); \
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register unsigned long r1 ASM_REG(1); \
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register unsigned long r2 ASM_REG(2); \
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register unsigned long r3 ASM_REG(3)
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register unsigned long arg0 ASM_REG(0) = (uint32_t)(a0)
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#define __declare_arg_1(a0, a1, res) \
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typeof(a1) __a1 = (a1); \
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struct arm_smccc_res *___res = (res); \
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register unsigned long r0 ASM_REG(0) = (uint32_t)(a0); \
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register unsigned long r1 ASM_REG(1) = __a1; \
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register unsigned long r2 ASM_REG(2); \
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register unsigned long r3 ASM_REG(3)
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register unsigned long arg0 ASM_REG(0) = (uint32_t)(a0);\
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register typeof(a1) arg1 ASM_REG(1) = __a1
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#define __declare_arg_2(a0, a1, a2, res) \
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typeof(a1) __a1 = (a1); \
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typeof(a2) __a2 = (a2); \
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struct arm_smccc_res *___res = (res); \
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register unsigned long r0 ASM_REG(0) = (uint32_t)(a0); \
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register unsigned long r1 ASM_REG(1) = __a1; \
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register unsigned long r2 ASM_REG(2) = __a2; \
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register unsigned long r3 ASM_REG(3)
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register unsigned long arg0 ASM_REG(0) = (uint32_t)(a0);\
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register typeof(a1) arg1 ASM_REG(1) = __a1; \
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register typeof(a2) arg2 ASM_REG(2) = __a2
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#define __declare_arg_3(a0, a1, a2, a3, res) \
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typeof(a1) __a1 = (a1); \
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typeof(a2) __a2 = (a2); \
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typeof(a3) __a3 = (a3); \
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struct arm_smccc_res *___res = (res); \
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register unsigned long r0 ASM_REG(0) = (uint32_t)(a0); \
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register unsigned long r1 ASM_REG(1) = __a1; \
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register unsigned long r2 ASM_REG(2) = __a2; \
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register unsigned long r3 ASM_REG(3) = __a3
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register unsigned long arg0 ASM_REG(0) = (uint32_t)(a0);\
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register typeof(a1) arg1 ASM_REG(1) = __a1; \
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register typeof(a2) arg2 ASM_REG(2) = __a2; \
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register typeof(a3) arg3 ASM_REG(3) = __a3
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#define __declare_arg_4(a0, a1, a2, a3, a4, res) \
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typeof(a4) __a4 = (a4); \
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__declare_arg_3(a0, a1, a2, a3, res); \
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register unsigned long r4 ASM_REG(4) = __a4
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register typeof(a4) arg4 ASM_REG(4) = __a4
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#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \
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typeof(a5) __a5 = (a5); \
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__declare_arg_4(a0, a1, a2, a3, a4, res); \
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register typeof(a5) r5 ASM_REG(5) = __a5
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register typeof(a5) arg5 ASM_REG(5) = __a5
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#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \
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typeof(a6) __a6 = (a6); \
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__declare_arg_5(a0, a1, a2, a3, a4, a5, res); \
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register typeof(a6) r6 ASM_REG(6) = __a6
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register typeof(a6) arg6 ASM_REG(6) = __a6
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#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \
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typeof(a7) __a7 = (a7); \
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__declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \
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register typeof(a7) r7 ASM_REG(7) = __a7
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register typeof(a7) arg7 ASM_REG(7) = __a7
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#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__)
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#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__)
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#define ___constraints(count) \
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: __constraint_write_ ## count \
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: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) \
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: __constraint_read_ ## count \
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: "memory"
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#define __constraints(count) ___constraints(count)
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@@ -204,6 +185,10 @@ struct arm_smccc_res {
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*/
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#define arm_smccc_1_1_smc(...) \
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do { \
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register unsigned long r0 ASM_REG(0); \
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register unsigned long r1 ASM_REG(1); \
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register unsigned long r2 ASM_REG(2); \
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register unsigned long r3 ASM_REG(3); \
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__declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \
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asm volatile("smc #0\n" \
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__constraints(__count_args(__VA_ARGS__))); \
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