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[IA64] more cleanup in vhpt.h
VHPT_CCHAIN_LOOKUP removed, body is now inlined in ivt.S vhpt_insert() is now written in C. Cleanup within vhpt.c/.h Signed-off-by: Tristan Gingold <tristan.gingold@bull.net>
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@@ -249,9 +249,21 @@ END(vhpt_miss)
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ENTRY(itlb_miss)
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DBG_FAULT(1)
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#ifdef XEN
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VHPT_CCHAIN_LOOKUP(itlb_miss,i)
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mov r31 = pr
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mov r16 = cr.ifa
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;;
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extr.u r17=r16,59,5
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;;
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/* If address belongs to VMM, go to alt tlb handler */
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cmp.eq p6,p0=0x1e,r17
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(p6) br.cond.spnt late_alt_itlb_miss
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;;
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cmp.eq p6,p0=0x1d,r17
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(p6) br.cond.spnt late_alt_itlb_miss
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;;
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mov pr = r31, 0x1ffff
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;;
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#ifdef VHPT_GLOBAL
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// br.cond.sptk page_fault
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br.cond.sptk fast_tlb_miss_reflect
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;;
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#endif
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@@ -301,14 +313,23 @@ END(itlb_miss)
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ENTRY(dtlb_miss)
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DBG_FAULT(2)
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#ifdef XEN
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VHPT_CCHAIN_LOOKUP(dtlb_miss,d)
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mov r31=pr
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mov r16=cr.ifa // get virtual address
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;;
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extr.u r17=r16,59,5
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;;
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/* If address belongs to VMM, go to alt tlb handler */
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cmp.eq p6,p0=0x1e,r17
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(p6) br.cond.spnt late_alt_dtlb_miss
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;;
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cmp.eq p6,p0=0x1d,r17
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(p6) br.cond.spnt late_alt_dtlb_miss
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;;
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#if VHPT_ENABLED
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// XXX TODO optimization
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mov r31=pr // save predicates
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mov r30=cr.ipsr
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mov r28=cr.iip
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mov r16=cr.ifa // get virtual address
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mov r17=cr.isr // save predicates
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mov r17=cr.isr
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;;
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extr.u r18 = r30, IA64_PSR_CPL0_BIT, 2 // extract psr.cpl
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@@ -413,13 +434,6 @@ END(dtlb_miss)
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// 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
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ENTRY(alt_itlb_miss)
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DBG_FAULT(3)
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#ifdef XEN
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//#ifdef VHPT_GLOBAL
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// VHPT_CCHAIN_LOOKUP(alt_itlb_miss,i)
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// br.cond.sptk page_fault
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// ;;
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//#endif
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#endif
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#ifdef XEN
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mov r31=pr
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mov r16=cr.ifa // get address that caused the TLB miss
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@@ -478,13 +492,6 @@ END(alt_itlb_miss)
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// 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
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ENTRY(alt_dtlb_miss)
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DBG_FAULT(4)
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#ifdef XEN
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//#ifdef VHPT_GLOBAL
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// VHPT_CCHAIN_LOOKUP(alt_dtlb_miss,d)
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// br.cond.sptk page_fault
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// ;;
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//#endif
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#endif
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#ifdef XEN
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mov r31=pr
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mov r16=cr.ifa // get address that caused the TLB miss
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@@ -15,6 +15,8 @@
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#include <asm/dma.h>
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#include <asm/vhpt.h>
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extern long running_on_sim;
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DEFINE_PER_CPU (unsigned long, vhpt_paddr);
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DEFINE_PER_CPU (unsigned long, vhpt_pend);
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@@ -101,16 +103,26 @@ static void vhpt_map(unsigned long pte)
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ia64_srlz_i();
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}
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void vhpt_insert (unsigned long vadr, unsigned long pte, unsigned long logps)
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{
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struct vhpt_lf_entry *vlfe = (struct vhpt_lf_entry *)ia64_thash(vadr);
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unsigned long tag = ia64_ttag (vadr);
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/* No need to first disable the entry, since VHPT is per LP
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and VHPT is TR mapped. */
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vlfe->itir = logps;
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vlfe->page_flags = pte | _PAGE_P;
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vlfe->ti_tag = tag;
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}
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void vhpt_multiple_insert(unsigned long vaddr, unsigned long pte, unsigned long logps)
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{
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unsigned long mask = (1L << logps) - 1;
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extern long running_on_sim;
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int i;
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if (logps-PAGE_SHIFT > 10 && !running_on_sim) {
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// if this happens, we may want to revisit this algorithm
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printf("vhpt_multiple_insert:logps-PAGE_SHIFT>10,spinning..\n");
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while(1);
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panic("vhpt_multiple_insert:logps-PAGE_SHIFT>10,spinning..\n");
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}
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if (logps-PAGE_SHIFT > 2) {
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// FIXME: Should add counter here to see how often this
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@@ -151,12 +163,9 @@ void vhpt_init(void)
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* from domain heap when each domain is created. Assume xen buddy
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* allocator can provide natural aligned page by order?
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*/
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// vhpt_imva = alloc_xenheap_pages(VHPT_SIZE_LOG2 - PAGE_SHIFT);
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page = alloc_domheap_pages(NULL, VHPT_SIZE_LOG2 - PAGE_SHIFT, 0);
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if (!page) {
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printf("vhpt_init: can't allocate VHPT!\n");
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while(1);
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}
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if (!page)
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panic("vhpt_init: can't allocate VHPT!\n");
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paddr = page_to_maddr(page);
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__get_cpu_var(vhpt_paddr) = paddr;
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__get_cpu_var(vhpt_pend) = paddr + vhpt_total_size - 1;
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@@ -182,7 +182,7 @@ GLOBAL_ENTRY(ia64_new_rr7)
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mov r21=loc6 // saved vhpt physical address
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;;
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or r23=r25,r21 // construct PA | page properties
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mov r24=VHPT_PAGE_SHIFT<<2
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mov r24=VHPT_SIZE_LOG2<<2
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;;
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ptr.d r22,r24
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;;
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@@ -504,19 +504,6 @@ stacked:
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br.ret.sptk.few rp
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END(pal_emulator_static)
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GLOBAL_ENTRY(vhpt_insert)
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// alloc loc0 = ar.pfs, 3, 1, 0, 0
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mov r16=r32
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mov r26=r33
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mov r27=r34
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;;
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VHPT_INSERT()
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// VHPT_INSERT1() ... add collision chains later
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// mov ar.pfs = loc0
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br.ret.sptk.few rp
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;;
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END(vhpt_insert)
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// These instructions are copied in the domains.
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// This is the virtual PAL, which simply does an hypercall.
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// The size is 2 bunldes (32 Bytes). It handles both static and stacked
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@@ -11,8 +11,6 @@
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/* Number of entries in the VHPT. The size of an entry is 4*8B == 32B */
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#define VHPT_NUM_ENTRIES (1 << (VHPT_SIZE_LOG2 - 5))
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#define VHPT_PAGE_SHIFT VHPT_SIZE_LOG2
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#ifdef CONFIG_SMP
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# define vhpt_flush_all() smp_vhpt_flush_all()
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#else
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@@ -46,8 +44,8 @@ extern void vhpt_flush_address_remote(int cpu, unsigned long vadr,
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unsigned long addr_range);
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extern void vhpt_multiple_insert(unsigned long vaddr, unsigned long pte,
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unsigned long logps);
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extern void vhpt_insert (unsigned long vadr, unsigned long ptr,
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unsigned logps);
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extern void vhpt_insert (unsigned long vadr, unsigned long pte,
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unsigned long logps);
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extern void vhpt_flush(void);
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extern void smp_vhpt_flush_all(void);
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@@ -56,59 +54,4 @@ DECLARE_PER_CPU (unsigned long, vhpt_paddr);
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DECLARE_PER_CPU (unsigned long, vhpt_pend);
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#endif /* !__ASSEMBLY */
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#if !VHPT_ENABLED
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#define VHPT_CCHAIN_LOOKUP(Name, i_or_d)
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#else
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// VHPT_CCHAIN_LOOKUP is intended to run with psr.i+ic off
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#define VHPT_CCHAIN_LOOKUP(Name, i_or_d) \
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\
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CC_##Name:; \
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mov r31 = pr; \
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mov r16 = cr.ifa; \
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;; \
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extr.u r17=r16,59,5 \
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;; \
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/* If address belongs to VMM, go to alt tlb handler */ \
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cmp.eq p6,p0=0x1e,r17; \
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(p6) br.cond.spnt late_alt_##Name \
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;; \
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cmp.eq p6,p0=0x1d,r17; \
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(p6) br.cond.spnt late_alt_##Name \
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;; \
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mov pr = r31, 0x1ffff; \
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;;
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/* r16 = vadr, r26 = pte, r27 = logps */
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#define VHPT_INSERT() \
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{.mmi; \
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thash r17 = r16; \
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or r26 = 1, r26; \
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nop 0; \
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;; \
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}; \
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{.mii; \
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ttag r21 = r16; \
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adds r18 = VLE_ITIR_OFFSET, r17; \
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adds r19 = VLE_PGFLAGS_OFFSET, r17; \
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;; \
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}; \
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{.mmi; \
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\
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st8[r18] = r27; \
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adds r20 = VLE_TITAG_OFFSET, r17; \
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nop 0; \
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;; \
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}; \
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{.mmb; \
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st8[r19] = r26; \
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st8[r20] = r21; \
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nop 0; \
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;; \
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}
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#endif /* VHPT_ENABLED */
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#endif
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