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xen/arm: traps: report level 0 faults in panic_PAR()
decode_fsc() derives the fault level from the low two bits of the FSC, so
level 0 is a valid output: FSC_FLT_TRANS is 0x04, i.e. "translation fault,
level 0 or translation table base register".
This is reachable on arm64 because xen_pgtable is the zeroeth-level root,
but fsc_level_str() has no case for it and prints " (level invalid)"
instead. At the time the function was created Xen used only three levels.
Add the missing case. On arm32 the zeroeth level does not exist but FSC
0 denotes address size fault at translation table base register.
While at it, make decode_fsc() decode also address size faults.
Signed-off-by: Michal Orzel <michal.orzel@amd.com>
Reviewed-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
(cherry picked from commit 4e1f58ea1a)
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@@ -513,6 +513,7 @@ extern register_t __cpu_logical_map[];
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/*
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* 543210 BIT
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* 00XXLL -- XX Fault Level LL
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* ..00LL -- Address Size Fault LL
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* ..01LL -- Translation Fault LL
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* ..10LL -- Access Fault LL
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* ..11LL -- Permission Fault LL
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@@ -526,6 +527,7 @@ extern register_t __cpu_logical_map[];
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#define FSC_TYPE_OTH (_AC(0x02,U)<<4)
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#define FSC_TYPE_IMPL (_AC(0x03,U)<<4)
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#define FSC_FLT_ADDR_SIZE (0x00)
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#define FSC_FLT_TRANS (0x04)
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#define FSC_FLT_ACCESS (0x08)
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#define FSC_FLT_PERM (0x0c)
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@@ -307,6 +307,10 @@ static const char *decode_fsc(uint32_t fsc, int *level)
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switch ( fsc & 0x3f )
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{
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case FSC_FLT_ADDR_SIZE ... FSC_FLT_ADDR_SIZE + 3:
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msg = "Address size fault";
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*level = fsc & FSC_LL_MASK;
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break;
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case FSC_FLT_TRANS ... FSC_FLT_TRANS + 3:
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msg = "Translation fault";
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*level = fsc & FSC_LL_MASK;
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@@ -363,6 +367,7 @@ static const char *fsc_level_str(int level)
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switch ( level )
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{
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case -1: return "";
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case 0: return " at level 0 or TTBR";
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case 1: return " at level 1";
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case 2: return " at level 2";
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case 3: return " at level 3";
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