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x86/time: relax barriers
On x86 there's no need for full barriers in loops waiting for some memory location to change. Nor do we need full barriers between two reads and two writes - SMP ones fully suffice. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
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1 parent
7676077a0a
commit
2fd44a3edc
1 file changed
+7
-7
+7
-7
@@ -1211,7 +1211,7 @@ static void tsc_check_slave(void *unused)
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unsigned int cpu = smp_processor_id();
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local_irq_disable();
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while ( !cpumask_test_cpu(cpu, &tsc_check_cpumask) )
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mb();
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cpu_relax();
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check_tsc_warp(cpu_khz, &tsc_max_warp);
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cpumask_clear_cpu(cpu, &tsc_check_cpumask);
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local_irq_enable();
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@@ -1276,7 +1276,7 @@ static void time_calibration_tsc_rendezvous(void *_r)
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if ( smp_processor_id() == 0 )
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{
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while ( atomic_read(&r->semaphore) != (total_cpus - 1) )
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mb();
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cpu_relax();
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if ( r->master_stime == 0 )
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{
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@@ -1289,21 +1289,21 @@ static void time_calibration_tsc_rendezvous(void *_r)
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write_tsc(r->master_tsc_stamp);
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while ( atomic_read(&r->semaphore) != (2*total_cpus - 1) )
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mb();
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cpu_relax();
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atomic_set(&r->semaphore, 0);
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}
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else
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{
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atomic_inc(&r->semaphore);
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while ( atomic_read(&r->semaphore) < total_cpus )
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mb();
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cpu_relax();
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if ( i == 0 )
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write_tsc(r->master_tsc_stamp);
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atomic_inc(&r->semaphore);
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while ( atomic_read(&r->semaphore) > total_cpus )
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mb();
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cpu_relax();
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}
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}
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@@ -1321,7 +1321,7 @@ static void time_calibration_std_rendezvous(void *_r)
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while ( atomic_read(&r->semaphore) != (total_cpus - 1) )
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cpu_relax();
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r->master_stime = read_platform_stime();
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mb(); /* write r->master_stime /then/ signal */
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smp_wmb(); /* write r->master_stime /then/ signal */
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atomic_inc(&r->semaphore);
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}
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else
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@@ -1329,7 +1329,7 @@ static void time_calibration_std_rendezvous(void *_r)
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atomic_inc(&r->semaphore);
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while ( atomic_read(&r->semaphore) != total_cpus )
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cpu_relax();
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mb(); /* receive signal /then/ read r->master_stime */
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smp_rmb(); /* receive signal /then/ read r->master_stime */
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}
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time_calibration_rendezvous_tail(r);
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