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ocaml: evtchn+xc bindings: use libxenctrl and libxenguest

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Now that tools/libxc is licensed under LGPL I don't think there is any need for
an LGPL reimplementation under tools/ocaml.

For the most part the conversion to the up-to-date libxc API (xc_lib.c
essentially implemented the same interface as an older libxc) was pretty
automatic. There are some functions which appear to no longer exist in libxc
which I therefore simply removed the bindings for and a small number of
interfaces which had changed.

Many of the functions bound by the stubs have no in-tree users (which I think
is fine for a language binding) so I have no way to confirm correctness other
than by eye. I was however able to confirm that oxenstored still worked and to
build a XCP toolstack which could successfully start a PV guest.

Uses the new XC_OPENFLAG_NON_REENTRANT option to avoid potential conflicts
between pthreads and the ocaml runtime.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Cc: Vincent Hanquez <Vincent.Hanquez@eu.citrix.com>
Committed-by: Ian Jackson <ian.jackson@eu.citrix.com>
This commit is contained in:
Ian Campbell committed 2011-01-06 17:37:00 +00:00
1 parent daec2beeaf
commit 30cbc3ec4b
16 files changed
+414 -2595
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tools/ocaml/Makefile.rules
+3 -3
View File
@@ -54,18 +54,18 @@ mk-caml-lib-bytecode = $(call quiet-command, $(OCAMLC) $(OCAMLCFLAGS) -a -o $1 $
mk-caml-stubs = $(call quiet-command, $(OCAMLMKLIB) -o `basename $1 .a` $2,MKLIB,$1)
mk-caml-lib-stubs = \
$(call quiet-command, $(AR) rcs $1 $2 && $(OCAMLMKLIB) -o `basename $1 .a | sed -e 's/^lib//'` $2,MKLIB,$1)
$(call quiet-command, $(AR) rcs $1 $2 && $(OCAMLMKLIB) -o `basename $1 .a | sed -e 's/^lib//'` $3 $2,MKLIB,$1)
# define a library target <name>.cmxa and <name>.cma
define OCAML_LIBRARY_template
$(1).cmxa: lib$(1)_stubs.a $(foreach obj,$($(1)_OBJS),$(obj).cmx)
$(call mk-caml-lib-native,$$@, -cclib -l$(1)_stubs, $(foreach obj,$($(1)_OBJS),$(obj).cmx))
$(call mk-caml-lib-native,$$@, -cclib -l$(1)_stubs $(foreach lib,$(LIBS_$(1)),-cclib $(lib)), $(foreach obj,$($(1)_OBJS),$(obj).cmx))
$(1).cma: $(foreach obj,$($(1)_OBJS),$(obj).cmo)
$(call mk-caml-lib-bytecode,$$@, -dllib dll$(1)_stubs.so -cclib -l$(1)_stubs, $$+)
$(1)_stubs.a: $(foreach obj,$$($(1)_C_OBJS),$(obj).o)
$(call mk-caml-stubs,$$@, $$+)
lib$(1)_stubs.a: $(foreach obj,$($(1)_C_OBJS),$(obj).o)
$(call mk-caml-lib-stubs,$$@, $$+)
$(call mk-caml-lib-stubs,$$@, $$+, $(LIBS_$(1)))
endef
define OCAML_NOC_LIBRARY_template
tools/ocaml/libs/eventchn/eventchn.ml
+10 -7
View File
@@ -16,12 +16,15 @@
exception Error of string
external init: unit -> Unix.file_descr = "stub_eventchn_init"
external notify: Unix.file_descr -> int -> unit = "stub_eventchn_notify"
external bind_interdomain: Unix.file_descr -> int -> int -> int = "stub_eventchn_bind_interdomain"
external bind_dom_exc_virq: Unix.file_descr -> int = "stub_eventchn_bind_dom_exc_virq"
external unbind: Unix.file_descr -> int -> unit = "stub_eventchn_unbind"
external read_port: Unix.file_descr -> int = "stub_eventchn_read_port"
external write_port: Unix.file_descr -> int -> unit = "stub_eventchn_write_port"
type handle
external init: unit -> handle = "stub_eventchn_init"
external fd: handle -> Unix.file_descr = "stub_eventchn_fd"
external notify: handle -> int -> unit = "stub_eventchn_notify"
external bind_interdomain: handle -> int -> int -> int = "stub_eventchn_bind_interdomain"
external bind_dom_exc_virq: handle -> int = "stub_eventchn_bind_dom_exc_virq"
external unbind: handle -> int -> unit = "stub_eventchn_unbind"
external pending: handle -> int = "stub_eventchn_pending"
external unmask: handle -> int -> unit = "stub_eventchn_unmask"
let _ = Callback.register_exception "eventchn.error" (Error "register_callback")
tools/ocaml/libs/eventchn/eventchn.mli
+13 -8
View File
@@ -15,12 +15,17 @@
*)
exception Error of string
external init : unit -> Unix.file_descr = "stub_eventchn_init"
external notify : Unix.file_descr -> int -> unit = "stub_eventchn_notify"
external bind_interdomain : Unix.file_descr -> int -> int -> int
type handle
external init : unit -> handle = "stub_eventchn_init"
external fd: handle -> Unix.file_descr = "stub_eventchn_fd"
external notify : handle -> int -> unit = "stub_eventchn_notify"
external bind_interdomain : handle -> int -> int -> int
= "stub_eventchn_bind_interdomain"
external bind_dom_exc_virq : Unix.file_descr -> int = "stub_eventchn_bind_dom_exc_virq"
external unbind : Unix.file_descr -> int -> unit = "stub_eventchn_unbind"
external read_port : Unix.file_descr -> int = "stub_eventchn_read_port"
external write_port : Unix.file_descr -> int -> unit
= "stub_eventchn_write_port"
external bind_dom_exc_virq : handle -> int = "stub_eventchn_bind_dom_exc_virq"
external unbind : handle -> int -> unit = "stub_eventchn_unbind"
external pending : handle -> int = "stub_eventchn_pending"
external unmask : handle -> int -> unit
= "stub_eventchn_unmask"
tools/ocaml/libs/eventchn/eventchn_stubs.c
+52 -61
View File
@@ -34,119 +34,110 @@
#include <caml/callback.h>
#include <caml/fail.h>
#define EVENTCHN_PATH "/dev/xen/evtchn"
#define _H(__h) ((xc_interface *)(__h))
static int do_ioctl(int handle, int cmd, void *arg)
CAMLprim value stub_eventchn_init(void)
{
return ioctl(handle, cmd, arg);
}
CAMLparam0();
CAMLlocal1(result);
static int do_read_port(int handle, evtchn_port_t *port)
{
return (read(handle, port, sizeof(evtchn_port_t)) != sizeof(evtchn_port_t));
}
static int do_write_port(int handle, evtchn_port_t port)
{
return (write(handle, &port, sizeof(evtchn_port_t)) != sizeof(evtchn_port_t));
}
int eventchn_do_open(void)
{
return open(EVENTCHN_PATH, O_RDWR);
}
CAMLprim value stub_eventchn_init(value unit)
{
CAMLparam1(unit);
int fd = eventchn_do_open();
if (fd == -1)
xc_interface *xce = xc_evtchn_open(NULL, XC_OPENFLAG_NON_REENTRANT);
if (xce == NULL)
caml_failwith("open failed");
CAMLreturn(Val_int(fd));
result = (value)xce;
CAMLreturn(result);
}
CAMLprim value stub_eventchn_notify(value fd, value port)
CAMLprim value stub_eventchn_fd(value xce)
{
CAMLparam2(fd, port);
struct ioctl_evtchn_notify notify;
CAMLparam1(xce);
CAMLlocal1(result);
int fd;
fd = xc_evtchn_fd(_H(xce));
if (fd == -1)
caml_failwith("evtchn fd failed");
result = Val_int(fd);
CAMLreturn(result);
}
CAMLprim value stub_eventchn_notify(value xce, value port)
{
CAMLparam2(xce, port);
int rc;
notify.port = Int_val(port);
rc = do_ioctl(Int_val(fd), IOCTL_EVTCHN_NOTIFY, &notify);
rc = xc_evtchn_notify(_H(xce), Int_val(port));
if (rc == -1)
caml_failwith("ioctl notify failed");
caml_failwith("evtchn notify failed");
CAMLreturn(Val_unit);
}
CAMLprim value stub_eventchn_bind_interdomain(value fd, value domid,
CAMLprim value stub_eventchn_bind_interdomain(value xce, value domid,
value remote_port)
{
CAMLparam3(fd, domid, remote_port);
CAMLparam3(xce, domid, remote_port);
CAMLlocal1(port);
struct ioctl_evtchn_bind_interdomain bind;
int rc;
evtchn_port_or_error_t rc;
bind.remote_domain = Int_val(domid);
bind.remote_port = Int_val(remote_port);
rc = do_ioctl(Int_val(fd), IOCTL_EVTCHN_BIND_INTERDOMAIN, &bind);
rc = xc_evtchn_bind_interdomain(_H(xce), Int_val(domid), Int_val(remote_port));
if (rc == -1)
caml_failwith("ioctl bind_interdomain failed");
caml_failwith("evtchn bind_interdomain failed");
port = Val_int(rc);
CAMLreturn(port);
}
CAMLprim value stub_eventchn_bind_dom_exc_virq(value fd)
CAMLprim value stub_eventchn_bind_dom_exc_virq(value xce)
{
CAMLparam1(fd);
CAMLparam1(xce);
CAMLlocal1(port);
struct ioctl_evtchn_bind_virq bind;
int rc;
evtchn_port_or_error_t rc;
bind.virq = VIRQ_DOM_EXC;
rc = do_ioctl(Int_val(fd), IOCTL_EVTCHN_BIND_VIRQ, &bind);
rc = xc_evtchn_bind_virq(_H(xce), VIRQ_DOM_EXC);
if (rc == -1)
caml_failwith("ioctl bind_virq failed");
caml_failwith("evtchn bind_dom_exc_virq failed");
port = Val_int(rc);
CAMLreturn(port);
}
CAMLprim value stub_eventchn_unbind(value fd, value port)
CAMLprim value stub_eventchn_unbind(value xce, value port)
{
CAMLparam2(fd, port);
struct ioctl_evtchn_unbind unbind;
CAMLparam2(xce, port);
int rc;
unbind.port = Int_val(port);
rc = do_ioctl(Int_val(fd), IOCTL_EVTCHN_UNBIND, &unbind);
rc = xc_evtchn_unbind(_H(xce), Int_val(port));
if (rc == -1)
caml_failwith("ioctl unbind failed");
caml_failwith("evtchn unbind failed");
CAMLreturn(Val_unit);
}
CAMLprim value stub_eventchn_read_port(value fd)
CAMLprim value stub_eventchn_pending(value xce)
{
CAMLparam1(fd);
CAMLparam1(xce);
CAMLlocal1(result);
evtchn_port_t port;
evtchn_port_or_error_t port;
if (do_read_port(Int_val(fd), &port))
caml_failwith("read port failed");
port = xc_evtchn_pending(_H(xce));
if (port == -1)
caml_failwith("evtchn pending failed");
result = Val_int(port);
CAMLreturn(result);
}
CAMLprim value stub_eventchn_write_port(value fd, value _port)
CAMLprim value stub_eventchn_unmask(value xce, value _port)
{
CAMLparam2(fd, _port);
CAMLparam2(xce, _port);
evtchn_port_t port;
port = Int_val(_port);
if (do_write_port(Int_val(fd), port))
caml_failwith("write port failed");
if (xc_evtchn_unmask(_H(xce), port))
caml_failwith("evtchn unmask failed");
CAMLreturn(Val_unit);
}
tools/ocaml/libs/xc/Makefile
+5 -3
View File
@@ -2,15 +2,17 @@ TOPLEVEL=../..
XEN_ROOT=$(TOPLEVEL)/../..
include $(TOPLEVEL)/common.make
CFLAGS += -I../mmap -I./
OCAMLINCLUDE += -I ../mmap -I ../uuid
CFLAGS += -I../mmap -I./ -I$(XEN_ROOT)/tools/libxc
OCAMLINCLUDE += -I ../mmap -I ../uuid -I $(XEN_ROOT)/tools/libxc
OBJS = xc
INTF = xc.cmi
LIBS = xc.cma xc.cmxa
LIBS_xc = -L$(XEN_ROOT)/tools/libxc -lxenctrl -lxenguest
xc_OBJS = $(OBJS)
xc_C_OBJS = xc_lib xc_stubs
xc_C_OBJS = xc_stubs
OCAML_LIBRARY = xc
tools/ocaml/libs/xc/xc.h
-186
View File
@@ -1,186 +0,0 @@
/*
* Copyright (C) 2006-2007 XenSource Ltd.
* Copyright (C) 2008 Citrix Ltd.
* Author Vincent Hanquez <vincent.hanquez@eu.citrix.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation; version 2.1 only. with the special
* exception on linking described in file LICENSE.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*/
#include <xen/xen.h>
#include <xen/memory.h>
#include <xen/sysctl.h>
#include <xen/domctl.h>
#include <xen/sched.h>
#include <xen/sysctl.h>
#include <xen/sys/privcmd.h>
#include <xen/version.h>
#include <xen/foreign/x86_32.h>
#include <xen/foreign/x86_64.h>
#include <xen/hvm/params.h>
#include "xc_e820.h"
typedef xen_domctl_getdomaininfo_t xc_domaininfo_t;
typedef xen_domctl_getvcpuinfo_t xc_vcpuinfo_t;
typedef xen_sysctl_physinfo_t xc_physinfo_t;
struct xc_core_header {
unsigned int xch_magic;
unsigned int xch_nr_vcpus;
unsigned int xch_nr_pages;
unsigned int xch_ctxt_offset;
unsigned int xch_index_offset;
unsigned int xch_pages_offset;
};
typedef union {
#if defined(__i386__) || defined(__x86_64__)
vcpu_guest_context_x86_64_t x64;
vcpu_guest_context_x86_32_t x32;
#endif
vcpu_guest_context_t c;
} vcpu_guest_context_any_t;
char * xc_error_get(void);
void xc_error_clear(void);
int xc_using_injection(void);
int xc_interface_open(void);
int xc_interface_close(int handle);
int xc_domain_create(int handle, unsigned int ssidref,
xen_domain_handle_t dhandle,
unsigned int flags, unsigned int *pdomid);
int xc_domain_pause(int handle, unsigned int domid);
int xc_domain_unpause(int handle, unsigned int domid);
int xc_domain_resume_fast(int handle, unsigned int domid);
int xc_domain_destroy(int handle, unsigned int domid);
int xc_domain_shutdown(int handle, int domid, int reason);
int xc_vcpu_setaffinity(int handle, unsigned int domid, int vcpu,
uint64_t cpumap);
int xc_vcpu_getaffinity(int handle, unsigned int domid, int vcpu,
uint64_t *cpumap);
int xc_domain_getinfolist(int handle, unsigned int first_domain,
unsigned int max_domains, xc_domaininfo_t *info);
int xc_domain_getinfo(int handle, unsigned int first_domain,
xc_domaininfo_t *info);
int xc_domain_setmaxmem(int handle, unsigned int domid, unsigned int max_memkb);
int xc_domain_set_memmap_limit(int handle, unsigned int domid,
unsigned long map_limitkb);
int xc_domain_set_time_offset(int handle, unsigned int domid, int time_offset);
int xc_domain_memory_increase_reservation(int handle, unsigned int domid,
unsigned long nr_extents,
unsigned int extent_order,
unsigned int address_bits,
xen_pfn_t *extent_start);
int xc_domain_memory_decrease_reservation(int handle, unsigned int domid,
unsigned long nr_extents,
unsigned int extent_order,
unsigned int address_bits,
xen_pfn_t *extent_start);
int xc_domain_memory_populate_physmap(int handle, unsigned int domid,
unsigned long nr_extents,
unsigned int extent_order,
unsigned int address_bits,
xen_pfn_t *extent_start);
int xc_domain_setvmxassist(int handle, unsigned int domid, int use_vmxassist);
int xc_domain_max_vcpus(int handle, unsigned int domid, unsigned int max);
int xc_domain_sethandle(int handle, unsigned int domid,
xen_domain_handle_t dhandle);
int xc_vcpu_getinfo(int handle, unsigned int domid, unsigned int vcpu,
xc_vcpuinfo_t *info);
int xc_domain_ioport_permission(int handle, unsigned int domid,
unsigned int first_port, unsigned int nr_ports,
unsigned int allow_access);
int xc_vcpu_setcontext(int handle, unsigned int domid,
unsigned int vcpu, vcpu_guest_context_any_t *ctxt);
int xc_vcpu_getcontext(int handle, unsigned int domid,
unsigned int vcpu, vcpu_guest_context_any_t *ctxt);
int xc_domain_irq_permission(int handle, unsigned int domid,
unsigned char pirq, unsigned char allow_access);
int xc_domain_iomem_permission(int handle, unsigned int domid,
unsigned long first_mfn, unsigned long nr_mfns,
unsigned char allow_access);
long long xc_domain_get_cpu_usage(int handle, unsigned int domid,
unsigned int vcpu);
void *xc_map_foreign_range(int handle, unsigned int domid,
int size, int prot, unsigned long mfn);
int xc_map_foreign_ranges(int handle, unsigned int domid,
privcmd_mmap_entry_t *entries, int nr);
int xc_readconsolering(int handle, char **pbuffer,
unsigned int *pnr_chars, int clear);
int xc_send_debug_keys(int handle, char *keys);
int xc_physinfo(int handle, xc_physinfo_t *put_info);
int xc_pcpu_info(
int handle, int max_cpus, xen_sysctl_cpuinfo_t *info, int *nr_cpus);
int xc_sched_id(int handle, int *sched_id);
int xc_version(int handle, int cmd, void *arg);
int xc_evtchn_alloc_unbound(int handle, unsigned int domid,
unsigned int remote_domid);
int xc_evtchn_reset(int handle, unsigned int domid);
int xc_sched_credit_domain_set(int handle, unsigned int domid,
struct xen_domctl_sched_credit *sdom);
int xc_sched_credit_domain_get(int handle, unsigned int domid,
struct xen_domctl_sched_credit *sdom);
int xc_shadow_allocation_get(int handle, unsigned int domid,
uint32_t *mb);
int xc_shadow_allocation_set(int handle, unsigned int domid,
uint32_t mb);
int xc_domain_get_pfn_list(int handle, unsigned int domid,
uint64_t *pfn_array, unsigned long max_pfns);
int xc_hvm_check_pvdriver(int handle, unsigned int domid);
int xc_domain_assign_device(int handle, unsigned int domid,
int domain, int bus, int slot, int func);
int xc_domain_deassign_device(int handle, unsigned int domid,
int domain, int bus, int slot, int func);
int xc_domain_test_assign_device(int handle, unsigned int domid,
int domain, int bus, int slot, int func);
int xc_domain_watchdog(int handle, int id, uint32_t timeout);
int xc_domain_set_machine_address_size(int xc, uint32_t domid, unsigned int width);
int xc_domain_get_machine_address_size(int xc, uint32_t domid);
int xc_domain_cpuid_set(int xc, unsigned int domid, int hvm,
uint32_t input, uint32_t oinput,
char *config[4], char *config_out[4]);
int xc_domain_cpuid_apply(int xc, unsigned int domid, int hvm);
int xc_cpuid_check(uint32_t input, uint32_t optsubinput,
char *config[4], char *config_out[4]);
int xc_domain_send_s3resume(int handle, unsigned int domid);
int xc_domain_set_vpt_align(int handle, unsigned int domid, int vpt_align);
int xc_domain_set_hpet(int handle, unsigned int domid, int hpet);
int xc_domain_set_timer_mode(int handle, unsigned int domid, int mode);
int xc_domain_get_acpi_s_state(int handle, unsigned int domid);
#if XEN_SYSCTL_INTERFACE_VERSION >= 6
#define SAFEDIV(a, b) (((b) > 0) ? (a) / (b) : (a))
#define COMPAT_FIELD_physinfo_get_nr_cpus(p) (p).nr_cpus
#define COMPAT_FIELD_physinfo_get_sockets_per_node(p) \
SAFEDIV((p).nr_cpus, ((p).threads_per_core * (p).cores_per_socket * (p).nr_nodes))
#else
#define COMPAT_FIELD_physinfo_get_nr_cpus(p) \
((p).threads_per_core * (p).sockets_per_node * \
(p).cores_per_socket * (p).threads_per_core)
#define COMPAT_FIELD_physinfo_get_sockets_per_node(p) (p).sockets_per_node
#endif
#if __XEN_LATEST_INTERFACE_VERSION__ >= 0x00030209
#define COMPAT_FIELD_ADDRESS_BITS mem_flags
#else
#define COMPAT_FIELD_ADDRESS_BITS address_bits
#endif
tools/ocaml/libs/xc/xc.ml
+7 -21
View File
@@ -107,7 +107,7 @@ external sizeof_xen_pfn: unit -> int = "stub_sizeof_xen_pfn"
external interface_open: unit -> handle = "stub_xc_interface_open"
external interface_close: handle -> unit = "stub_xc_interface_close"
external using_injection: unit -> bool = "stub_xc_using_injection"
external is_fake: unit -> bool = "stub_xc_interface_is_fake"
let with_intf f =
let xc = interface_open () in
@@ -127,9 +127,6 @@ external _domain_sethandle: handle -> domid -> int array -> unit
let domain_sethandle handle n uuid =
_domain_sethandle handle n (Uuid.int_array_of_uuid uuid)
external domain_setvmxassist: handle -> domid -> bool -> unit
= "stub_xc_domain_setvmxassist"
external domain_max_vcpus: handle -> domid -> int -> unit
= "stub_xc_domain_max_vcpus"
@@ -165,9 +162,9 @@ external domain_iomem_permission: handle -> domid -> nativeint -> nativeint -> b
external domain_irq_permission: handle -> domid -> int -> bool -> unit
= "stub_xc_domain_irq_permission"
external vcpu_affinity_set: handle -> domid -> int -> int64 -> unit
external vcpu_affinity_set: handle -> domid -> int -> bool array -> unit
= "stub_xc_vcpu_setaffinity"
external vcpu_affinity_get: handle -> domid -> int -> int64
external vcpu_affinity_get: handle -> domid -> int -> bool array
= "stub_xc_vcpu_getaffinity"
external vcpu_context_get: handle -> domid -> int -> string
@@ -207,13 +204,13 @@ external domain_set_machine_address_size: handle -> domid -> int -> unit
external domain_get_machine_address_size: handle -> domid -> int
= "stub_xc_domain_get_machine_address_size"
external domain_cpuid_set: handle -> domid -> bool -> (int64 * (int64 option))
external domain_cpuid_set: handle -> domid -> (int64 * (int64 option))
-> string option array
-> string option array
= "stub_xc_domain_cpuid_set"
external domain_cpuid_apply: handle -> domid -> bool -> unit
= "stub_xc_domain_cpuid_apply"
external cpuid_check: (int64 * (int64 option)) -> string option array -> (bool * string option array)
external domain_cpuid_apply_policy: handle -> domid -> unit
= "stub_xc_domain_cpuid_apply_policy"
external cpuid_check: handle -> (int64 * (int64 option)) -> string option array -> (bool * string option array)
= "stub_xc_cpuid_check"
external map_foreign_range: handle -> domid -> int
@@ -230,17 +227,6 @@ external domain_deassign_device: handle -> domid -> (int * int * int * int) -> u
external domain_test_assign_device: handle -> domid -> (int * int * int * int) -> bool
= "stub_xc_domain_test_assign_device"
external domain_set_timer_mode: handle -> domid -> int -> unit = "stub_xc_domain_set_timer_mode"
external domain_set_hpet: handle -> domid -> int -> unit = "stub_xc_domain_set_hpet"
external domain_set_vpt_align: handle -> domid -> int -> unit = "stub_xc_domain_set_vpt_align"
external domain_send_s3resume: handle -> domid -> unit = "stub_xc_domain_send_s3resume"
external domain_get_acpi_s_state: handle -> domid -> int = "stub_xc_domain_get_acpi_s_state"
(** check if some hvm domain got pv driver or not *)
external hvm_check_pvdriver: handle -> domid -> bool
= "stub_xc_hvm_check_pvdriver"
external version: handle -> version = "stub_xc_version_version"
external version_compile_info: handle -> compile_info
= "stub_xc_version_compile_info"
tools/ocaml/libs/xc/xc.mli
+7 -19
View File
@@ -71,7 +71,7 @@ external sizeof_vcpu_guest_context : unit -> int
= "stub_sizeof_vcpu_guest_context"
external sizeof_xen_pfn : unit -> int = "stub_sizeof_xen_pfn"
external interface_open : unit -> handle = "stub_xc_interface_open"
external using_injection : unit -> bool = "stub_xc_using_injection"
external is_fake : unit -> bool = "stub_xc_interface_is_fake"
external interface_close : handle -> unit = "stub_xc_interface_close"
val with_intf : (handle -> 'a) -> 'a
external _domain_create : handle -> int32 -> domain_create_flag list -> int array -> domid
@@ -80,8 +80,6 @@ val domain_create : handle -> int32 -> domain_create_flag list -> 'a Uuid.t -> d
external _domain_sethandle : handle -> domid -> int array -> unit
= "stub_xc_domain_sethandle"
val domain_sethandle : handle -> domid -> 'a Uuid.t -> unit
external domain_setvmxassist: handle -> domid -> bool -> unit
= "stub_xc_domain_setvmxassist"
external domain_max_vcpus : handle -> domid -> int -> unit
= "stub_xc_domain_max_vcpus"
external domain_pause : handle -> domid -> unit = "stub_xc_domain_pause"
@@ -104,9 +102,9 @@ external domain_iomem_permission: handle -> domid -> nativeint -> nativeint -> b
= "stub_xc_domain_iomem_permission"
external domain_irq_permission: handle -> domid -> int -> bool -> unit
= "stub_xc_domain_irq_permission"
external vcpu_affinity_set : handle -> domid -> int -> int64 -> unit
external vcpu_affinity_set : handle -> domid -> int -> bool array -> unit
= "stub_xc_vcpu_setaffinity"
external vcpu_affinity_get : handle -> domid -> int -> int64
external vcpu_affinity_get : handle -> domid -> int -> bool array
= "stub_xc_vcpu_getaffinity"
external vcpu_context_get : handle -> domid -> int -> string
= "stub_xc_vcpu_context_get"
@@ -147,16 +145,6 @@ external domain_deassign_device: handle -> domid -> (int * int * int * int) -> u
external domain_test_assign_device: handle -> domid -> (int * int * int * int) -> bool
= "stub_xc_domain_test_assign_device"
external domain_set_timer_mode: handle -> domid -> int -> unit = "stub_xc_domain_set_timer_mode"
external domain_set_hpet: handle -> domid -> int -> unit = "stub_xc_domain_set_hpet"
external domain_set_vpt_align: handle -> domid -> int -> unit = "stub_xc_domain_set_vpt_align"
external domain_send_s3resume: handle -> domid -> unit
= "stub_xc_domain_send_s3resume"
external domain_get_acpi_s_state: handle -> domid -> int = "stub_xc_domain_get_acpi_s_state"
external hvm_check_pvdriver : handle -> domid -> bool
= "stub_xc_hvm_check_pvdriver"
external version : handle -> version = "stub_xc_version_version"
external version_compile_info : handle -> compile_info
= "stub_xc_version_compile_info"
@@ -185,12 +173,12 @@ external domain_set_machine_address_size: handle -> domid -> int -> unit
external domain_get_machine_address_size: handle -> domid -> int
= "stub_xc_domain_get_machine_address_size"
external domain_cpuid_set: handle -> domid -> bool -> (int64 * (int64 option))
external domain_cpuid_set: handle -> domid -> (int64 * (int64 option))
-> string option array
-> string option array
= "stub_xc_domain_cpuid_set"
external domain_cpuid_apply: handle -> domid -> bool -> unit
= "stub_xc_domain_cpuid_apply"
external cpuid_check: (int64 * (int64 option)) -> string option array -> (bool * string option array)
external domain_cpuid_apply_policy: handle -> domid -> unit
= "stub_xc_domain_cpuid_apply_policy"
external cpuid_check: handle -> (int64 * (int64 option)) -> string option array -> (bool * string option array)
= "stub_xc_cpuid_check"
tools/ocaml/libs/xc/xc_cpufeature.h
-116
View File
@@ -1,116 +0,0 @@
#ifndef __LIBXC_CPUFEATURE_H
#define __LIBXC_CPUFEATURE_H
/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
#define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
#define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
#define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
#define X86_FEATURE_DS (0*32+21) /* Debug Store */
#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
/* of FPU context), and CR4.OSFXSR available */
#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */
#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
#define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
#define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
#define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
/* Don't duplicate feature flags which are redundant with Intel! */
#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
#define X86_FEATURE_MP (1*32+19) /* MP Capable. */
#define X86_FEATURE_NX (1*32+20) /* Execute Disable */
#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
#define X86_FEATURE_FFXSR (1*32+25) /* FFXSR instruction optimizations */
#define X86_FEATURE_PAGE1GB (1*32+26) /* 1Gb large page support */
#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
#define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
#define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
#define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
/* Other features, Linux-defined mapping, word 3 */
/* This range is used for feature bits which conflict or are synthesized */
#define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
#define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
/* cpu types for specific tunings: */
#define X86_FEATURE_K8 (3*32+ 4) /* Opteron, Athlon64 */
#define X86_FEATURE_K7 (3*32+ 5) /* Athlon */
#define X86_FEATURE_P3 (3*32+ 6) /* P3 */
#define X86_FEATURE_P4 (3*32+ 7) /* P4 */
#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
#define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
#define X86_FEATURE_VMXE (4*32+ 5) /* Virtual Machine Extensions */
#define X86_FEATURE_SMXE (4*32+ 6) /* Safer Mode Extensions */
#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */
#define X86_FEATURE_CID (4*32+10) /* Context ID */
#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
#define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */
#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
#define X86_FEATURE_SSE4_1 (4*32+19) /* Streaming SIMD Extensions 4.1 */
#define X86_FEATURE_SSE4_2 (4*32+20) /* Streaming SIMD Extensions 4.2 */
#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running under some hypervisor */
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */
#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */
#define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */
#define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
#define X86_FEATURE_PHE (5*32+ 10) /* PadLock Hash Engine */
#define X86_FEATURE_PHE_EN (5*32+ 11) /* PHE enabled */
#define X86_FEATURE_PMM (5*32+ 12) /* PadLock Montgomery Multiplier */
#define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */
/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
#define X86_FEATURE_SVME (6*32+ 2) /* Secure Virtual Machine */
#define X86_FEATURE_EXTAPICSPACE (6*32+ 3) /* Extended APIC space */
#define X86_FEATURE_ALTMOVCR (6*32+ 4) /* LOCK MOV CR accesses CR+8 */
#define X86_FEATURE_ABM (6*32+ 5) /* Advanced Bit Manipulation */
#define X86_FEATURE_SSE4A (6*32+ 6) /* AMD Streaming SIMD Extensions-4a */
#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE Access */
#define X86_FEATURE_3DNOWPF (6*32+ 8) /* 3DNow! Prefetch */
#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
#define X86_FEATURE_IBS (6*32+ 10) /* Instruction Based Sampling */
#define X86_FEATURE_SSE5 (6*32+ 11) /* AMD Streaming SIMD Extensions-5 */
#define X86_FEATURE_SKINIT (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */
#define X86_FEATURE_WDT (6*32+ 13) /* Watchdog Timer */
#endif /* __LIBXC_CPUFEATURE_H */
tools/ocaml/libs/xc/xc_cpuid.h
-285
View File
@@ -1,285 +0,0 @@
#ifndef XC_CPUID_H
#define XC_CPUID_H
#ifdef XEN_DOMCTL_set_cpuid
#include "xc_cpufeature.h"
#define bitmaskof(idx) (1u << ((idx) & 31))
#define clear_bit(idx, dst) ((dst) &= ~(1u << ((idx) & 31)))
#define set_bit(idx, dst) ((dst) |= (1u << ((idx) & 31)))
#define DEF_MAX_BASE 0x00000004u
#define DEF_MAX_EXT 0x80000008u
static void xc_cpuid(uint32_t eax, uint32_t ecx, uint32_t regs[4])
{
unsigned int realecx = (ecx == XEN_CPUID_INPUT_UNUSED) ? 0 : ecx;
asm (
#ifdef __i386__
"push %%ebx; cpuid; mov %%ebx,%1; pop %%ebx"
#else
"push %%rbx; cpuid; mov %%ebx,%1; pop %%rbx"
#endif
: "=a" (regs[0]), "=r" (regs[1]), "=c" (regs[2]), "=d" (regs[3])
: "0" (eax), "2" (realecx));
}
enum { CPU_BRAND_INTEL, CPU_BRAND_AMD, CPU_BRAND_UNKNOWN };
static int xc_cpuid_brand_get(void)
{
uint32_t regs[4];
char str[13];
uint32_t *istr = (uint32_t *) str;
xc_cpuid(0, 0, regs);
istr[0] = regs[1];
istr[1] = regs[3];
istr[2] = regs[2];
str[12] = '\0';
if (strcmp(str, "AuthenticAMD") == 0) {
return CPU_BRAND_AMD;
} else if (strcmp(str, "GenuineIntel") == 0) {
return CPU_BRAND_INTEL;
} else
return CPU_BRAND_UNKNOWN;
}
static int hypervisor_is_64bit(int xc)
{
xen_capabilities_info_t xen_caps;
return ((xc_version(xc, XENVER_capabilities, &xen_caps) == 0) &&
(strstr(xen_caps, "x86_64") != NULL));
}
static void do_hvm_cpuid_policy(int xc, int domid, uint32_t input, uint32_t regs[4])
{
unsigned long is_pae;
int brand;
/* pae ? */
xc_get_hvm_param(xc, domid, HVM_PARAM_PAE_ENABLED, &is_pae);
is_pae = !!is_pae;
switch (input) {
case 0x00000000:
if (regs[0] > DEF_MAX_BASE)
regs[0] = DEF_MAX_BASE;
break;
case 0x00000001:
regs[2] &= (bitmaskof(X86_FEATURE_XMM3) |
bitmaskof(X86_FEATURE_SSSE3) |
bitmaskof(X86_FEATURE_CX16) |
bitmaskof(X86_FEATURE_SSE4_1) |
bitmaskof(X86_FEATURE_SSE4_2) |
bitmaskof(X86_FEATURE_POPCNT));
regs[2] |= bitmaskof(X86_FEATURE_HYPERVISOR);
regs[3] &= (bitmaskof(X86_FEATURE_FPU) |
bitmaskof(X86_FEATURE_VME) |
bitmaskof(X86_FEATURE_DE) |
bitmaskof(X86_FEATURE_PSE) |
bitmaskof(X86_FEATURE_TSC) |
bitmaskof(X86_FEATURE_MSR) |
bitmaskof(X86_FEATURE_PAE) |
bitmaskof(X86_FEATURE_MCE) |
bitmaskof(X86_FEATURE_CX8) |
bitmaskof(X86_FEATURE_APIC) |
bitmaskof(X86_FEATURE_SEP) |
bitmaskof(X86_FEATURE_MTRR) |
bitmaskof(X86_FEATURE_PGE) |
bitmaskof(X86_FEATURE_MCA) |
bitmaskof(X86_FEATURE_CMOV) |
bitmaskof(X86_FEATURE_PAT) |
bitmaskof(X86_FEATURE_CLFLSH) |
bitmaskof(X86_FEATURE_MMX) |
bitmaskof(X86_FEATURE_FXSR) |
bitmaskof(X86_FEATURE_XMM) |
bitmaskof(X86_FEATURE_XMM2));
/* We always support MTRR MSRs. */
regs[3] |= bitmaskof(X86_FEATURE_MTRR);
if (!is_pae)
clear_bit(X86_FEATURE_PAE, regs[3]);
break;
case 0x80000000:
if (regs[0] > DEF_MAX_EXT)
regs[0] = DEF_MAX_EXT;
break;
case 0x80000001:
if (!is_pae)
clear_bit(X86_FEATURE_NX, regs[3]);
break;
case 0x80000008:
regs[0] &= 0x0000ffffu;
regs[1] = regs[2] = regs[3] = 0;
break;
case 0x00000002: /* Intel cache info (dumped by AMD policy) */
case 0x00000004: /* Intel cache info (dumped by AMD policy) */
case 0x80000002: /* Processor name string */
case 0x80000003: /* ... continued */
case 0x80000004: /* ... continued */
case 0x80000005: /* AMD L1 cache/TLB info (dumped by Intel policy) */
case 0x80000006: /* AMD L2/3 cache/TLB info ; Intel L2 cache features */
break;
default:
regs[0] = regs[1] = regs[2] = regs[3] = 0;
break;
}
brand = xc_cpuid_brand_get();
if (brand == CPU_BRAND_AMD) {
switch (input) {
case 0x00000001:
/* Mask Intel-only features. */
regs[2] &= ~(bitmaskof(X86_FEATURE_SSSE3) |
bitmaskof(X86_FEATURE_SSE4_1) |
bitmaskof(X86_FEATURE_SSE4_2));
break;
case 0x00000002:
case 0x00000004:
regs[0] = regs[1] = regs[2] = 0;
break;
case 0x80000001: {
int is_64bit = hypervisor_is_64bit(xc) && is_pae;
if (!is_pae)
clear_bit(X86_FEATURE_PAE, regs[3]);
clear_bit(X86_FEATURE_PSE36, regs[3]);
/* Filter all other features according to a whitelist. */
regs[2] &= ((is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0) |
bitmaskof(X86_FEATURE_ALTMOVCR) |
bitmaskof(X86_FEATURE_ABM) |
bitmaskof(X86_FEATURE_SSE4A) |
bitmaskof(X86_FEATURE_MISALIGNSSE) |
bitmaskof(X86_FEATURE_3DNOWPF));
regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */
(is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
(is_64bit ? bitmaskof(X86_FEATURE_LM) : 0) |
bitmaskof(X86_FEATURE_SYSCALL) |
bitmaskof(X86_FEATURE_MP) |
bitmaskof(X86_FEATURE_MMXEXT) |
bitmaskof(X86_FEATURE_FFXSR) |
bitmaskof(X86_FEATURE_3DNOW) |
bitmaskof(X86_FEATURE_3DNOWEXT));
break;
}
}
} else if (brand == CPU_BRAND_INTEL) {
switch (input) {
case 0x00000001:
/* Mask AMD-only features. */
regs[2] &= ~(bitmaskof(X86_FEATURE_POPCNT));
break;
case 0x00000004:
regs[0] &= 0x3FF;
regs[3] &= 0x3FF;
break;
case 0x80000001:
{
int is_64bit = hypervisor_is_64bit(xc) && is_pae;
/* Only a few features are advertised in Intel's 0x80000001. */
regs[2] &= (is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0);
regs[3] &= ((is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
(is_64bit ? bitmaskof(X86_FEATURE_LM) : 0) |
(is_64bit ? bitmaskof(X86_FEATURE_SYSCALL) : 0));
break;
}
case 0x80000005:
{
regs[0] = regs[1] = regs[2] = 0;
break;
}
}
}
}
static void do_pv_cpuid_policy(int xc, int domid, uint32_t input, uint32_t regs[4])
{
int brand;
int guest_64_bits, xen_64_bits;
int ret;
ret = xc_domain_get_machine_address_size(xc, domid);
if (ret < 0)
return;
guest_64_bits = (ret == 64);
xen_64_bits = hypervisor_is_64bit(xc);
brand = xc_cpuid_brand_get();
if ((input & 0x7fffffff) == 1) {
clear_bit(X86_FEATURE_VME, regs[3]);
clear_bit(X86_FEATURE_PSE, regs[3]);
clear_bit(X86_FEATURE_PGE, regs[3]);
clear_bit(X86_FEATURE_MCE, regs[3]);
clear_bit(X86_FEATURE_MCA, regs[3]);
clear_bit(X86_FEATURE_MTRR, regs[3]);
clear_bit(X86_FEATURE_PSE36, regs[3]);
}
switch (input) {
case 1:
if (!xen_64_bits || brand == CPU_BRAND_AMD)
clear_bit(X86_FEATURE_SEP, regs[3]);
clear_bit(X86_FEATURE_DS, regs[3]);
clear_bit(X86_FEATURE_ACC, regs[3]);
clear_bit(X86_FEATURE_PBE, regs[3]);
clear_bit(X86_FEATURE_DTES64, regs[2]);
clear_bit(X86_FEATURE_MWAIT, regs[2]);
clear_bit(X86_FEATURE_DSCPL, regs[2]);
clear_bit(X86_FEATURE_VMXE, regs[2]);
clear_bit(X86_FEATURE_SMXE, regs[2]);
clear_bit(X86_FEATURE_EST, regs[2]);
clear_bit(X86_FEATURE_TM2, regs[2]);
if (!guest_64_bits)
clear_bit(X86_FEATURE_CX16, regs[2]);
clear_bit(X86_FEATURE_XTPR, regs[2]);
clear_bit(X86_FEATURE_PDCM, regs[2]);
clear_bit(X86_FEATURE_DCA, regs[2]);
break;
case 0x80000001:
if (!guest_64_bits) {
clear_bit(X86_FEATURE_LM, regs[3]);
clear_bit(X86_FEATURE_LAHF_LM, regs[2]);
if (brand != CPU_BRAND_AMD)
clear_bit(X86_FEATURE_SYSCALL, regs[3]);
} else
set_bit(X86_FEATURE_SYSCALL, regs[3]);
clear_bit(X86_FEATURE_PAGE1GB, regs[3]);
clear_bit(X86_FEATURE_RDTSCP, regs[3]);
clear_bit(X86_FEATURE_SVME, regs[2]);
clear_bit(X86_FEATURE_OSVW, regs[2]);
clear_bit(X86_FEATURE_IBS, regs[2]);
clear_bit(X86_FEATURE_SKINIT, regs[2]);
clear_bit(X86_FEATURE_WDT, regs[2]);
break;
case 5: /* MONITOR/MWAIT */
case 0xa: /* Architectural Performance Monitor Features */
case 0x8000000a: /* SVM revision and features */
case 0x8000001b: /* Instruction Based Sampling */
regs[0] = regs[1] = regs[2] = regs[3] = 0;
break;
}
}
static void do_cpuid_policy(int xc, int domid, int hvm, uint32_t input, uint32_t regs[4])
{
if (hvm)
do_hvm_cpuid_policy(xc, domid, input, regs);
else
do_pv_cpuid_policy(xc, domid, input, regs);
}
#endif
#endif
tools/ocaml/libs/xc/xc_e820.h
-20
View File
@@ -1,20 +0,0 @@
#ifndef __XC_E820_H__
#define __XC_E820_H__
#include <xen/hvm/e820.h>
/*
* PC BIOS standard E820 types and structure.
*/
#define E820_RAM 1
#define E820_RESERVED 2
#define E820_ACPI 3
#define E820_NVS 4
struct e820entry {
uint64_t addr;
uint64_t size;
uint32_t type;
} __attribute__((packed));
#endif /* __XC_E820_H__ */
tools/ocaml/libs/xc/xc_lib.c
-1537
View File
File diff suppressed because it is too large. Load diff
tools/ocaml/libs/xc/xc_stubs.c
+301 -315
View File
File diff suppressed because it is too large. Load diff
tools/ocaml/xenstored/Makefile
+2 -1
View File
@@ -39,7 +39,8 @@ XENSTOREDLIBS = \
-ccopt -L -ccopt $(OCAML_TOPLEVEL)/libs/log $(OCAML_TOPLEVEL)/libs/log/log.cmxa \
-ccopt -L -ccopt $(OCAML_TOPLEVEL)/libs/eventchn $(OCAML_TOPLEVEL)/libs/eventchn/eventchn.cmxa \
-ccopt -L -ccopt $(OCAML_TOPLEVEL)/libs/xc $(OCAML_TOPLEVEL)/libs/xc/xc.cmxa \
-ccopt -L -ccopt $(OCAML_TOPLEVEL)/libs/xb $(OCAML_TOPLEVEL)/libs/xb/xb.cmxa
-ccopt -L -ccopt $(OCAML_TOPLEVEL)/libs/xb $(OCAML_TOPLEVEL)/libs/xb/xb.cmxa \
-ccopt -L -ccopt $(XEN_ROOT)/tools/libxc
PROGRAMS = oxenstored
tools/ocaml/xenstored/event.ml
+9 -8
View File
@@ -16,14 +16,15 @@
(**************** high level binding ****************)
type t = {
fd: Unix.file_descr;
handle: Eventchn.handle;
mutable virq_port: int;
}
let init () = { fd = Eventchn.init (); virq_port = -1; }
let bind_dom_exc_virq eventchn = eventchn.virq_port <- Eventchn.bind_dom_exc_virq eventchn.fd
let bind_interdomain eventchn domid port = Eventchn.bind_interdomain eventchn.fd domid port
let unbind eventchn port = Eventchn.unbind eventchn.fd port
let notify eventchn port = Eventchn.notify eventchn.fd port
let read_port eventchn = Eventchn.read_port eventchn.fd
let write_port eventchn port = Eventchn.write_port eventchn.fd port
let init () = { handle = Eventchn.init (); virq_port = -1; }
let fd eventchn = Eventchn.fd eventchn.handle
let bind_dom_exc_virq eventchn = eventchn.virq_port <- Eventchn.bind_dom_exc_virq eventchn.handle
let bind_interdomain eventchn domid port = Eventchn.bind_interdomain eventchn.handle domid port
let unbind eventchn port = Eventchn.unbind eventchn.handle port
let notify eventchn port = Eventchn.notify eventchn.handle port
let pending eventchn = Eventchn.pending eventchn.handle
let unmask eventchn port = Eventchn.unmask eventchn.handle port
tools/ocaml/xenstored/xenstored.ml
+5 -5
View File
@@ -282,7 +282,7 @@ let _ =
Store.mkdir store (Perms.Connection.create 0) localpath;
if cf.domain_init then (
let usingxiu = Xc.using_injection () in
let usingxiu = Xc.is_fake () in
Connections.add_domain cons (Domains.create0 usingxiu domains);
Event.bind_dom_exc_virq eventchn
);
@@ -298,7 +298,7 @@ let _ =
let spec_fds =
(match rw_sock with None -> [] | Some x -> [ x ]) @
(match ro_sock with None -> [] | Some x -> [ x ]) @
(if cf.domain_init then [ eventchn.Event.fd ] else [])
(if cf.domain_init then [ Event.fd eventchn ] else [])
in
let xc = Xc.interface_open () in
@@ -309,7 +309,7 @@ let _ =
debug "new connection through socket";
Connections.add_anonymous cons cfd can_write
and handle_eventchn fd =
let port = Event.read_port eventchn in
let port = Event.pending eventchn in
finally (fun () ->
if port = eventchn.Event.virq_port then (
let (notify, deaddom) = Domains.cleanup xc domains in
@@ -317,14 +317,14 @@ let _ =
if deaddom <> [] || notify then
Connections.fire_spec_watches cons "@releaseDomain"
)
) (fun () -> Event.write_port eventchn port);
) (fun () -> Event.unmask eventchn port);
and do_if_set fd set fct =
if List.mem fd set then
fct fd in
maybe (fun fd -> do_if_set fd rset (accept_connection true)) rw_sock;
maybe (fun fd -> do_if_set fd rset (accept_connection false)) ro_sock;
do_if_set eventchn.Event.fd rset (handle_eventchn)
do_if_set (Event.fd eventchn) rset (handle_eventchn)
in
let last_stat_time = ref 0. in
Reference in new issue
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