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xen/arm: gic: Make sure the number of interrupt lines is valid before using it
GICv2 and GICv3 supports up to 1020 interrupts. However, the value computed from GICD_TYPER.ITLinesNumber can be up to 1024. On GICv3, we will end up to write in reserved registers that are right after the IROUTERs one as the value is not capped early enough. Cap the number of interrupts as soon as we compute it so we know we can safely using it afterwards. Signed-off-by: Julien Grall <julien.grall@arm.com> Reported-by: Jan-Peter Larsson <Jan-Peter.Larsson@arm.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Release-Acked-by: Juergen Gross <jgross@suse.com>
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@@ -353,6 +353,10 @@ static void __init gicv2_dist_init(void)
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type = readl_gicd(GICD_TYPER);
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nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1);
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/* Only 1020 interrupts are supported */
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nr_lines = min(1020U, nr_lines);
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gicv2_info.nr_lines = nr_lines;
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gic_cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5);
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printk("GICv2: %d lines, %d cpu%s%s (IID %8.8x).\n",
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nr_lines, gic_cpus, (gic_cpus == 1) ? "" : "s",
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@@ -377,9 +381,6 @@ static void __init gicv2_dist_init(void)
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for ( i = 32; i < nr_lines; i += 32 )
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writel_gicd(~0x0, GICD_ICENABLER + (i / 32) * 4);
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/* Only 1020 interrupts are supported */
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gicv2_info.nr_lines = min(1020U, nr_lines);
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/* Turn on the distributor */
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writel_gicd(GICD_CTL_ENABLE, GICD_CTLR);
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}
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@@ -607,6 +607,10 @@ static void __init gicv3_dist_init(void)
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if ( type & GICD_TYPE_LPIS )
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gicv3_lpi_init_host_lpis(GICD_TYPE_ID_BITS(type));
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/* Only 1020 interrupts are supported */
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nr_lines = min(1020U, nr_lines);
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gicv3_info.nr_lines = nr_lines;
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printk("GICv3: %d lines, (IID %8.8x).\n",
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nr_lines, readl_relaxed(GICD + GICD_IIDR));
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@@ -646,9 +650,6 @@ static void __init gicv3_dist_init(void)
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for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
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writeq_relaxed(affinity, GICD + GICD_IROUTER + i * 8);
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/* Only 1020 interrupts are supported */
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gicv3_info.nr_lines = min(1020U, nr_lines);
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}
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static int gicv3_enable_redist(void)
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