x86: Define APIC_TIMER_MODE_xxx in apicdef.h

Signed-off-by: Wei Gang <gang.wei@intel.com>

xen/arch/x86/apic.c

@@ -38,11 +38,6 @@
 #include <mach_apic.h>
 #include <io_ports.h>
 
-#define APIC_TIMER_MODE_ONESHOT         (0 << 17)
-#define APIC_TIMER_MODE_PERIODIC        (1 << 17)
-#define APIC_TIMER_MODE_TSC_DEADLINE    (2 << 17)
-#define APIC_TIMER_MODE_MASK            (3 << 17)
-
 static int tdt_enabled __read_mostly;
 static int tdt_enable __initdata = 1;
 boolean_param("tdt", tdt_enable);
@@ -1163,7 +1158,7 @@ static void __setup_APIC_LVTT(unsigned int clocks)
 
     ver = GET_APIC_VERSION(apic_read(APIC_LVR));
     /* NB. Xen uses local APIC timer in one-shot mode. */
-    lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
+    lvtt_value = /*APIC_TIMER_MODE_PERIODIC |*/ LOCAL_TIMER_VECTOR;
     if (!APIC_INTEGRATED(ver))
         lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
 

xen/arch/x86/hvm/vlapic.c

@@ -56,7 +56,7 @@
 static unsigned int vlapic_lvt_mask[VLAPIC_LVT_NUM] =
 {
      /* LVTT */
-     LVT_MASK | APIC_LVT_TIMER_PERIODIC,
+     LVT_MASK | APIC_TIMER_MODE_PERIODIC,
      /* LVTTHMR */
      LVT_MASK | APIC_MODE_MASK,
      /* LVTPC */
@@ -79,7 +79,7 @@ static unsigned int vlapic_lvt_mask[VLAPIC_LVT_NUM] =
     (vlapic_get_reg(vlapic, lvt_type) & APIC_MODE_MASK)
 
 #define vlapic_lvtt_period(vlapic)                              \
-    (vlapic_get_reg(vlapic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC)
+    (vlapic_get_reg(vlapic, APIC_LVTT) & APIC_TIMER_MODE_PERIODIC)
 
 
 /*

xen/include/asm-x86/apicdef.h

@@ -90,7 +90,10 @@
 #define			APIC_TIMER_BASE_CLKIN		0x0
 #define			APIC_TIMER_BASE_TMBASE		0x1
 #define			APIC_TIMER_BASE_DIV		0x2
-#define			APIC_LVT_TIMER_PERIODIC		(1<<17)
+#define			APIC_TIMER_MODE_MASK		(0x3<<17)
+#define			APIC_TIMER_MODE_ONESHOT		(0x0<<17)
+#define			APIC_TIMER_MODE_PERIODIC	(0x1<<17)
+#define			APIC_TIMER_MODE_TSC_DEADLINE	(0x2<<17)
 #define			APIC_LVT_MASKED			(1<<16)
 #define			APIC_LVT_LEVEL_TRIGGER		(1<<15)
 #define			APIC_LVT_REMOTE_IRR		(1<<14)