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x86/vioapic: bind interrupts to PVH Dom0
Add the glue in order to bind the PVH Dom0 GSI from bare metal. This is done when Dom0 unmasks the vIO APIC pins, by fetching the current pin settings and setting up the PIRQ, which will then be bound to Dom0. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
This commit is contained in:
1 parent
fba0049426
commit
3e68095ef9
1 file changed
+60
@@ -158,6 +158,52 @@ static int vioapic_read(
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return X86EMUL_OKAY;
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}
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static int vioapic_hwdom_map_gsi(unsigned int gsi, unsigned int trig,
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unsigned int pol)
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{
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struct domain *currd = current->domain;
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xen_domctl_bind_pt_irq_t pt_irq_bind = {
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.irq_type = PT_IRQ_TYPE_PCI,
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.machine_irq = gsi,
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};
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int ret, pirq = gsi;
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ASSERT(is_hardware_domain(currd));
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/* Interrupt has been unmasked, bind it now. */
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ret = mp_register_gsi(gsi, trig, pol);
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if ( ret == -EEXIST )
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return 0;
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if ( ret )
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{
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gprintk(XENLOG_WARNING, "vioapic: error registering GSI %u: %d\n",
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gsi, ret);
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return ret;
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}
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ret = allocate_and_map_gsi_pirq(currd, pirq, &pirq);
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if ( ret )
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{
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gprintk(XENLOG_WARNING, "vioapic: error mapping GSI %u: %d\n",
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gsi, ret);
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return ret;
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}
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pcidevs_lock();
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ret = pt_irq_create_bind(currd, &pt_irq_bind);
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if ( ret )
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{
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gprintk(XENLOG_WARNING, "vioapic: error binding GSI %u: %d\n",
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gsi, ret);
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spin_lock(&currd->event_lock);
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unmap_domain_pirq(currd, pirq);
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spin_unlock(&currd->event_lock);
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}
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pcidevs_unlock();
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return ret;
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}
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static void vioapic_write_redirent(
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struct hvm_vioapic *vioapic, unsigned int idx,
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int top_word, uint32_t val)
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@@ -190,6 +236,20 @@ static void vioapic_write_redirent(
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*pent = ent;
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if ( is_hardware_domain(d) && unmasked )
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{
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int ret;
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ret = vioapic_hwdom_map_gsi(gsi, ent.fields.trig_mode,
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ent.fields.polarity);
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if ( ret )
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{
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/* Mask the entry again. */
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pent->fields.mask = 1;
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unmasked = 0;
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}
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}
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if ( gsi == 0 )
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{
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vlapic_adjust_i8259_target(d);
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