x86/Intel: add support for Haswell CPU models

... according to their most recent public documentation.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
master commit: 3e787021fb
master date: 2013-08-27 11:15:15 +0200

xen/arch/x86/acpi/cpu_idle.c

@@ -135,8 +135,10 @@ static void do_get_hw_residencies(void *arg)
     case 0x3A:
     case 0x3E:
     /* Haswell */
-    case 0x3c:
+    case 0x3C:
+    case 0x3F:
     case 0x45:
+    case 0x46:
         GET_PC2_RES(hw_res->pc2);
         GET_CC7_RES(hw_res->cc7);
         /* fall through */

xen/arch/x86/hvm/vmx/vmx.c

@@ -1801,7 +1801,7 @@ static const struct lbr_info *last_branch_msr_get(void)
         /* Ivy Bridge */
         case 58: case 62:
         /* Haswell */
-        case 60: case 69:
+        case 60: case 63: case 69: case 70:
             return nh_lbr;
             break;
         /* Atom */

xen/arch/x86/hvm/vmx/vpmu_core2.c

@@ -878,7 +878,12 @@ int vmx_vpmu_initialise(struct vcpu *v, unsigned int vpmu_flags)
 
         case 0x3a: /* IvyBridge */
         case 0x3e: /* IvyBridge EP */
-        case 0x3c: /* Haswell */
+
+        /* Haswell: */
+        case 0x3c:
+        case 0x3f:
+        case 0x45:
+        case 0x46:
             ret = core2_vpmu_initialise(v, vpmu_flags);
             if ( !ret )
                 vpmu->arch_vpmu_ops = &core2_vpmu_ops;