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ARM/vgic: Clean up vgic_v{2,3}_setup_hw()
vgic_v{2,3}_setup_hw()'s callers are __init, so they should be too.
vgic_v{2,3}_hw and gic_v2_hw_data are written once during init and
unmodified thereafter, so make them __ro_after_init. Reposition
'bool enabled' in these structures to fit in the tail padding, removing
8 bytes from their size when paddr_t is 8B.
While at it, drop dead vgic_v3_setup_hw() dummy implementation
from vgic/vgic.c. GICV3 depends on !NEW_VGIC.
No functional change.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Michal Orzel <michal.orzel@amd.com>
Reviewed-by: Julien Grall <julien@xen.org>
This commit is contained in:
Andrew Cooper authored and Michal Orzel committed
1 parent
79225a0c77
commit
452ee45ee1
4 files changed
+13
-25
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@@ -25,7 +25,6 @@
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#include <asm/vreg.h>
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static struct {
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bool enabled;
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/* Distributor interface address */
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paddr_t dbase;
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/* CPU interface address & size */
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@@ -36,10 +35,11 @@ static struct {
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/* Offset to add to get an 8kB contiguous region if GIC is aliased */
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uint32_t aliased_offset;
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} vgic_v2_hw;
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bool enabled;
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} vgic_v2_hw __ro_after_init;
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void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize,
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paddr_t vbase, uint32_t aliased_offset)
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void __init vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize,
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paddr_t vbase, uint32_t aliased_offset)
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{
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vgic_v2_hw.enabled = true;
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vgic_v2_hw.dbase = dbase;
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@@ -44,19 +44,18 @@
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#define VGICD_CTLR_DEFAULT (GICD_CTLR_ARE_NS)
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static struct {
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bool enabled;
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/* Distributor interface address */
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paddr_t dbase;
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/* Re-distributor regions */
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unsigned int nr_rdist_regions;
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const struct rdist_region *regions;
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unsigned int intid_bits; /* Number of interrupt ID bits */
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} vgic_v3_hw;
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bool enabled;
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} vgic_v3_hw __ro_after_init;
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void vgic_v3_setup_hw(paddr_t dbase,
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unsigned int nr_rdist_regions,
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const struct rdist_region *regions,
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unsigned int intid_bits)
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void __init vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions,
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const struct rdist_region *regions,
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unsigned int intid_bits)
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{
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vgic_v3_hw.enabled = true;
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vgic_v3_hw.dbase = dbase;
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@@ -24,7 +24,6 @@
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#include "vgic.h"
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static struct {
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bool enabled;
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paddr_t dbase; /* Distributor interface address */
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paddr_t cbase; /* CPU interface address & size */
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paddr_t csize;
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@@ -32,10 +31,11 @@ static struct {
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/* Offset to add to get an 8kB contiguous region if GIC is aliased */
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uint32_t aliased_offset;
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} gic_v2_hw_data;
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bool enabled;
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} gic_v2_hw_data __ro_after_init;
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void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize,
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paddr_t vbase, uint32_t aliased_offset)
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void __init vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize,
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paddr_t vbase, uint32_t aliased_offset)
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{
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gic_v2_hw_data.enabled = true;
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gic_v2_hw_data.dbase = dbase;
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@@ -964,17 +964,6 @@ unsigned int vgic_max_vcpus(unsigned int domctl_vgic_version)
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}
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}
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#ifdef CONFIG_GICV3
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/* Dummy implementation to allow building without actual vGICv3 support. */
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void vgic_v3_setup_hw(paddr_t dbase,
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unsigned int nr_rdist_regions,
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const struct rdist_region *regions,
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unsigned int intid_bits)
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{
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panic("New VGIC implementation does not yet support GICv3\n");
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}
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#endif
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/*
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* Local variables:
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* mode: C
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