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xen: arm: extend HSR struct definitions to 64-bit
The main change is that the 4-bit register specifiers are extended to 5 bits by taking in an adjacent SBZP bit. Also 64-bit has two other properties indicting whether or not the target register was 64-bit (x<n>) or 32-bit (w<n>) and whether the instruction has acquire/release semantics. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Tim Deegan <tim@xen.org>
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+12
-8
@@ -99,11 +99,11 @@ union hsr {
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unsigned long ec:6; /* Exception Class */
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};
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/* reg, reg0, reg1 are 4 bits on AArch32, the fifth bit is sbzp. */
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struct hsr_cp32 {
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unsigned long read:1; /* Direction */
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unsigned long crm:4; /* CRm */
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unsigned long reg:4; /* Rt */
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unsigned long sbzp:1;
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unsigned long reg:5; /* Rt */
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unsigned long crn:4; /* CRn */
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unsigned long op1:3; /* Op1 */
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unsigned long op2:3; /* Op2 */
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@@ -116,10 +116,9 @@ union hsr {
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struct hsr_cp64 {
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unsigned long read:1; /* Direction */
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unsigned long crm:4; /* CRm */
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unsigned long reg1:4; /* Rt1 */
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unsigned long sbzp1:1;
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unsigned long reg2:4; /* Rt2 */
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unsigned long sbzp2:2;
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unsigned long reg1:5; /* Rt1 */
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unsigned long reg2:5; /* Rt2 */
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unsigned long sbzp2:1;
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unsigned long op1:4; /* Op1 */
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unsigned long cc:4; /* Condition Code */
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unsigned long ccvalid:1;/* CC Valid */
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@@ -133,9 +132,14 @@ union hsr {
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unsigned long s1ptw:1; /* */
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unsigned long cache:1; /* Cache Maintenance */
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unsigned long eat:1; /* External Abort Type */
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#ifdef CONFIG_ARM_32
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unsigned long sbzp0:6;
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unsigned long reg:4; /* Register */
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unsigned long sbzp1:1;
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#else
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unsigned long sbzp0:4;
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unsigned long ar:1; /* Acquire Release */
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unsigned long sf:1; /* Sixty Four bit register */
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#endif
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unsigned long reg:5; /* Register */
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unsigned long sign:1; /* Sign extend */
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unsigned long size:2; /* Access Size */
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unsigned long valid:1; /* Syndrome Valid */
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