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x86/msr: Start cleaning up msr-index.h
Make a start on cleaning up the constants in msr-index.h. No functional change - only formatting changes. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
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@@ -1,7 +1,74 @@
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#ifndef __ASM_MSR_INDEX_H
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#define __ASM_MSR_INDEX_H
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/* CPU model specific register (MSR) numbers */
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/*
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* CPU model specific register (MSR) numbers
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*
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* Definitions for an MSR should follow this style:
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*
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* #define MSR_$NAME 0x$INDEX
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* #define $NAME_$FIELD1 (_AC($X, ULL) << $POS1)
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* #define $NAME_$FIELD2 (_AC($Y, ULL) << $POS2)
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*
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* Blocks of related constants should be sorted by MSR index. The constant
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* names should be as concise as possible, and the bit names may have an
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* abbreviated name. Exceptions will be considered on a case-by-case basis.
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*/
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#define MSR_APIC_BASE 0x0000001b
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#define APIC_BASE_BSP (_AC(1, ULL) << 8)
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#define APIC_BASE_EXTD (_AC(1, ULL) << 10)
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#define APIC_BASE_ENABLE (_AC(1, ULL) << 11)
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#define APIC_BASE_ADDR_MASK 0x000ffffffffff000ULL
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#define MSR_TEST_CTRL 0x00000033
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#define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29)
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#define TEST_CTRL_SPLITLOCK_DISABLE (_AC(1, ULL) << 31)
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#define MSR_INTEL_CORE_THREAD_COUNT 0x00000035
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#define MSR_CTC_THREAD_MASK 0x0000ffff
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#define MSR_CTC_CORE_MASK 0xffff0000
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#define MSR_SPEC_CTRL 0x00000048
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#define SPEC_CTRL_IBRS (_AC(1, ULL) << 0)
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#define SPEC_CTRL_STIBP (_AC(1, ULL) << 1)
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#define SPEC_CTRL_SSBD (_AC(1, ULL) << 2)
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#define MSR_PRED_CMD 0x00000049
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#define PRED_CMD_IBPB (_AC(1, ULL) << 0)
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#define MSR_PPIN_CTL 0x0000004e
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#define PPIN_LOCKOUT (_AC(1, ULL) << 0)
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#define PPIN_ENABLE (_AC(1, ULL) << 1)
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#define MSR_PPIN 0x0000004f
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#define MSR_CORE_CAPABILITIES 0x000000cf
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#define CORE_CAPS_SPLITLOCK_DETECT (_AC(1, ULL) << 5)
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#define MSR_ARCH_CAPABILITIES 0x0000010a
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#define ARCH_CAPS_RDCL_NO (_AC(1, ULL) << 0)
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#define ARCH_CAPS_IBRS_ALL (_AC(1, ULL) << 1)
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#define ARCH_CAPS_RSBA (_AC(1, ULL) << 2)
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#define ARCH_CAPS_SKIP_L1DFL (_AC(1, ULL) << 3)
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#define ARCH_CAPS_SSB_NO (_AC(1, ULL) << 4)
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#define ARCH_CAPS_MDS_NO (_AC(1, ULL) << 5)
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#define ARCH_CAPS_IF_PSCHANGE_MC_NO (_AC(1, ULL) << 6)
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#define ARCH_CAPS_TSX_CTRL (_AC(1, ULL) << 7)
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#define ARCH_CAPS_TAA_NO (_AC(1, ULL) << 8)
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#define MSR_FLUSH_CMD 0x0000010b
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#define FLUSH_CMD_L1D (_AC(1, ULL) << 0)
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#define MSR_TSX_FORCE_ABORT 0x0000010f
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#define TSX_FORCE_ABORT_RTM (_AC(1, ULL) << 0)
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#define MSR_TSX_CTRL 0x00000122
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#define TSX_CTRL_RTM_DISABLE (_AC(1, ULL) << 0)
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#define TSX_CTRL_CPUID_CLEAR (_AC(1, ULL) << 1)
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/*
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* Legacy MSR constants in need of cleanup. No new MSRs below this comment.
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*/
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/* x86-64 specific MSRs */
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#define MSR_EFER 0xc0000080 /* extended feature register */
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@@ -32,54 +99,6 @@
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#define EFER_KNOWN_MASK (EFER_SCE | EFER_LME | EFER_LMA | EFER_NX | \
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EFER_SVME | EFER_FFXSE)
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#define MSR_TEST_CTRL 0x00000033
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#define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29)
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#define TEST_CTRL_SPLITLOCK_DISABLE (_AC(1, ULL) << 31)
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#define MSR_INTEL_CORE_THREAD_COUNT 0x00000035
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#define MSR_CTC_THREAD_MASK 0x0000ffff
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#define MSR_CTC_CORE_MASK 0xffff0000
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/* Speculation Controls. */
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#define MSR_SPEC_CTRL 0x00000048
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#define SPEC_CTRL_IBRS (_AC(1, ULL) << 0)
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#define SPEC_CTRL_STIBP (_AC(1, ULL) << 1)
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#define SPEC_CTRL_SSBD (_AC(1, ULL) << 2)
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#define MSR_PRED_CMD 0x00000049
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#define PRED_CMD_IBPB (_AC(1, ULL) << 0)
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/* Intel Protected Processor Inventory Number */
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#define MSR_PPIN_CTL 0x0000004e
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#define MSR_PPIN 0x0000004f
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#define PPIN_LOCKOUT (_AC(1, ULL) << 0)
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#define PPIN_ENABLE (_AC(1, ULL) << 1)
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#define MSR_CORE_CAPABILITIES 0x000000cf
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#define CORE_CAPS_SPLITLOCK_DETECT (_AC(1, ULL) << 5)
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#define MSR_ARCH_CAPABILITIES 0x0000010a
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#define ARCH_CAPS_RDCL_NO (_AC(1, ULL) << 0)
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#define ARCH_CAPS_IBRS_ALL (_AC(1, ULL) << 1)
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#define ARCH_CAPS_RSBA (_AC(1, ULL) << 2)
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#define ARCH_CAPS_SKIP_L1DFL (_AC(1, ULL) << 3)
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#define ARCH_CAPS_SSB_NO (_AC(1, ULL) << 4)
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#define ARCH_CAPS_MDS_NO (_AC(1, ULL) << 5)
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#define ARCH_CAPS_IF_PSCHANGE_MC_NO (_AC(1, ULL) << 6)
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#define ARCH_CAPS_TSX_CTRL (_AC(1, ULL) << 7)
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#define ARCH_CAPS_TAA_NO (_AC(1, ULL) << 8)
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#define MSR_FLUSH_CMD 0x0000010b
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#define FLUSH_CMD_L1D (_AC(1, ULL) << 0)
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#define MSR_TSX_FORCE_ABORT 0x0000010f
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#define TSX_FORCE_ABORT_RTM (_AC(1, ULL) << 0)
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#define MSR_TSX_CTRL 0x00000122
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#define TSX_CTRL_RTM_DISABLE (_AC(1, ULL) << 0)
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#define TSX_CTRL_CPUID_CLEAR (_AC(1, ULL) << 1)
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/* Intel MSRs. Some also available on other CPUs */
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#define MSR_IA32_PERFCTR0 0x000000c1
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#define MSR_IA32_A_PERFCTR0 0x000004c1
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@@ -359,12 +378,6 @@
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#define MSR_IA32_TSC_ADJUST 0x0000003b
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#define MSR_APIC_BASE 0x0000001b
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#define APIC_BASE_BSP (1<<8)
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#define APIC_BASE_EXTD (1<<10)
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#define APIC_BASE_ENABLE (1<<11)
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#define APIC_BASE_ADDR_MASK 0x000ffffffffff000ul
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#define MSR_X2APIC_FIRST 0x00000800
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#define MSR_X2APIC_LAST 0x00000bff
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