bitkeeper revision 1.1691.1.13 (42a767bfQ0_UVkV0FEMxkQeSluJPmA)

More irq changes: moving towards addressing irqs by vector rather than
'irq index'.
Signed-off-by: Keir Fraser <keir@xensource.com>

xen/arch/x86/acpi/boot.c

@@ -88,22 +88,6 @@ EXPORT_SYMBOL(x86_acpiid_to_apicid);
  */
 enum acpi_irq_model_id		acpi_irq_model = ACPI_IRQ_MODEL_PIC;
 
-#if 0/*def	CONFIG_X86_64*/
-
-/* rely on all ACPI tables being in the direct mapping */
-char *__acpi_map_table(unsigned long phys_addr, unsigned long size)
-{
-	if (!phys_addr || !size)
-	return NULL;
-
-	if (phys_addr < (end_pfn_map << PAGE_SHIFT))
-		return __va(phys_addr);
-
-	return NULL;
-}
-
-#else
-
 /*
  * Temporarily use the virtual area starting from FIX_IO_APIC_BASE_END,
  * to map the target physical address. The problem is that set_fixmap()
@@ -143,7 +127,6 @@ char *__acpi_map_table(unsigned long phys, unsigned long size)
 
 	return ((char *) base + offset);
 }
-#endif
 
 #ifdef CONFIG_PCI_MMCONFIG
 static int __init acpi_parse_mcfg(unsigned long phys_addr, unsigned long size)
@@ -289,42 +272,6 @@ acpi_parse_ioapic (
 	return 0;
 }
 
-#ifdef CONFIG_ACPI_INTERPRETER
-/*
- * Parse Interrupt Source Override for the ACPI SCI
- */
-static void
-acpi_sci_ioapic_setup(u32 gsi, u16 polarity, u16 trigger)
-{
-	if (trigger == 0)	/* compatible SCI trigger is level */
-		trigger = 3;
-
-	if (polarity == 0)	/* compatible SCI polarity is low */
-		polarity = 3;
-
-	/* Command-line over-ride via acpi_sci= */
-	if (acpi_sci_flags.trigger)
-		trigger = acpi_sci_flags.trigger;
-
-	if (acpi_sci_flags.polarity)
-		polarity = acpi_sci_flags.polarity;
-
-	/*
- 	 * mp_config_acpi_legacy_irqs() already setup IRQs < 16
-	 * If GSI is < 16, this will update its flags,
-	 * else it will create a new mp_irqs[] entry.
-	 */
-	mp_override_legacy_irq(gsi, polarity, trigger, gsi);
-
-	/*
-	 * stash over-ride to indicate we've been here
-	 * and for later update of acpi_fadt
-	 */
-	acpi_sci_override_gsi = gsi;
-	return;
-}
-#endif
-
 static int __init
 acpi_parse_int_src_ovr (
 	acpi_table_entry_header *header, const unsigned long end)
@@ -338,14 +285,6 @@ acpi_parse_int_src_ovr (
 
 	acpi_table_print_madt_entry(header);
 
-#ifdef CONFIG_ACPI_INTERPRETER
-	if (intsrc->bus_irq == acpi_fadt.sci_int) {
-		acpi_sci_ioapic_setup(intsrc->global_irq,
-			intsrc->flags.polarity, intsrc->flags.trigger);
-		return 0;
-	}
-#endif
-
 	if (acpi_skip_timer_override &&
 		intsrc->bus_irq == 0 && intsrc->global_irq == 2) {
 			printk(PREFIX "BIOS IRQ0 pin2 override ignored.\n");
@@ -382,122 +321,6 @@ acpi_parse_nmi_src (
 
 #endif /* CONFIG_X86_IO_APIC */
 
-#ifdef	CONFIG_ACPI_BUS
-
-/*
- * acpi_pic_sci_set_trigger()
- * 
- * use ELCR to set PIC-mode trigger type for SCI
- *
- * If a PIC-mode SCI is not recognized or gives spurious IRQ7's
- * it may require Edge Trigger -- use "acpi_sci=edge"
- *
- * Port 0x4d0-4d1 are ECLR1 and ECLR2, the Edge/Level Control Registers
- * for the 8259 PIC.  bit[n] = 1 means irq[n] is Level, otherwise Edge.
- * ECLR1 is IRQ's 0-7 (IRQ 0, 1, 2 must be 0)
- * ECLR2 is IRQ's 8-15 (IRQ 8, 13 must be 0)
- */
-
-void __init
-acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
-{
-	unsigned int mask = 1 << irq;
-	unsigned int old, new;
-
-	/* Real old ELCR mask */
-	old = inb(0x4d0) | (inb(0x4d1) << 8);
-
-	/*
-	 * If we use ACPI to set PCI irq's, then we should clear ELCR
-	 * since we will set it correctly as we enable the PCI irq
-	 * routing.
-	 */
-	new = acpi_noirq ? old : 0;
-
-	/*
-	 * Update SCI information in the ELCR, it isn't in the PCI
-	 * routing tables..
-	 */
-	switch (trigger) {
-	case 1:	/* Edge - clear */
-		new &= ~mask;
-		break;
-	case 3: /* Level - set */
-		new |= mask;
-		break;
-	}
-
-	if (old == new)
-		return;
-
-	printk(PREFIX "setting ELCR to %04x (from %04x)\n", new, old);
-	outb(new, 0x4d0);
-	outb(new >> 8, 0x4d1);
-}
-
-
-#endif /* CONFIG_ACPI_BUS */
-
-int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
-{
-#ifdef CONFIG_X86_IO_APIC
-	if (use_pci_vector() && !platform_legacy_irq(gsi))
- 		*irq = IO_APIC_VECTOR(gsi);
-	else
-#endif
-		*irq = gsi;
-	return 0;
-}
-
-unsigned int acpi_register_gsi(u32 gsi, int edge_level, int active_high_low)
-{
-	unsigned int irq;
-	unsigned int plat_gsi = gsi;
-
-#ifdef CONFIG_PCI
-	/*
-	 * Make sure all (legacy) PCI IRQs are set as level-triggered.
-	 */
-	if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
-		extern void eisa_set_level_irq(unsigned int irq);
-
-		if (edge_level == ACPI_LEVEL_SENSITIVE)
-				eisa_set_level_irq(gsi);
-	}
-#endif
-
-#ifdef CONFIG_X86_IO_APIC
-	if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) {
-		plat_gsi = mp_register_gsi(gsi, edge_level, active_high_low);
-	}
-#endif
-	acpi_gsi_to_irq(plat_gsi, &irq);
-	return irq;
-}
-EXPORT_SYMBOL(acpi_register_gsi);
-
-/*
- *  ACPI based hotplug support for CPU
- */
-#ifdef CONFIG_ACPI_HOTPLUG_CPU
-int
-acpi_map_lsapic(acpi_handle handle, int *pcpu)
-{
-	/* TBD */
-	return -EINVAL;
-}
-EXPORT_SYMBOL(acpi_map_lsapic);
-
-
-int
-acpi_unmap_lsapic(int cpu)
-{
-	/* TBD */
-	return -EINVAL;
-}
-EXPORT_SYMBOL(acpi_unmap_lsapic);
-#endif /* CONFIG_ACPI_HOTPLUG_CPU */
-
 static unsigned long __init
 acpi_scan_rsdp (
 	unsigned long		start,

xen/arch/x86/i8259.c

@@ -35,13 +35,13 @@
 BUILD_COMMON_IRQ()
 
 #define BI(x,y) \
-	BUILD_IRQ(x##y)
+    BUILD_IRQ(x##y)
 
 #define BUILD_16_IRQS(x) \
-	BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
-	BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
-	BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
-	BI(x,c) BI(x,d) BI(x,e) BI(x,f)
+    BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
+    BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
+    BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
+    BI(x,c) BI(x,d) BI(x,e) BI(x,f)
 
 BUILD_16_IRQS(0x0) BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
@@ -57,11 +57,9 @@ BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
  * is no hardware IRQ pin equivalent for them, they are triggered
  * through the ICC by us (IPIs)
  */
-#ifdef CONFIG_SMP
 BUILD_SMP_INTERRUPT(event_check_interrupt,EVENT_CHECK_VECTOR)
 BUILD_SMP_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
 BUILD_SMP_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
-#endif
 
 /*
  * Every pentium local APIC has two 'local interrupts', with a
@@ -75,19 +73,19 @@ BUILD_SMP_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
 BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
 
 #define IRQ(x,y) \
-	IRQ##x##y##_interrupt
+    IRQ##x##y##_interrupt
 
 #define IRQLIST_16(x) \
-	IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
-	IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
-	IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
-	IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
+    IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
+    IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
+    IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
+    IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
 
     static void (*interrupt[])(void) = {
-	IRQLIST_16(0x0), IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
-	IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
-	IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
-	IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
+        IRQLIST_16(0x0), IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
+        IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
+        IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
+        IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
     };
 
 #undef IRQ
@@ -104,31 +102,38 @@ BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
 
 spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
 
-static void end_8259A_irq (unsigned int irq)
+static void disable_8259A_vector(unsigned int vector)
 {
-    if (!(irq_desc[irq_to_vector(irq)].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
-        enable_8259A_irq(irq);
+    disable_8259A_irq(LEGACY_IRQ_FROM_VECTOR(vector));
 }
 
-#define shutdown_8259A_irq	disable_8259A_irq
+static void enable_8259A_vector(unsigned int vector)
+{
+    enable_8259A_irq(LEGACY_IRQ_FROM_VECTOR(vector));
+}
 
-void mask_and_ack_8259A(unsigned int);
+static void mask_and_ack_8259A_vector(unsigned int);
 
-static unsigned int startup_8259A_irq(unsigned int irq)
+static void end_8259A_vector(unsigned int vector)
+{
+    if (!(irq_desc[vector].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+        enable_8259A_vector(vector);
+}
+
+static unsigned int startup_8259A_vector(unsigned int vector)
 { 
-    enable_8259A_irq(irq);
+    enable_8259A_vector(vector);
     return 0; /* never anything pending */
 }
 
 static struct hw_interrupt_type i8259A_irq_type = {
-    "XT-PIC",
-    startup_8259A_irq,
-    shutdown_8259A_irq,
-    enable_8259A_irq,
-    disable_8259A_irq,
-    mask_and_ack_8259A,
-    end_8259A_irq,
-    NULL
+    .typename = "XT-PIC",
+    .startup  = startup_8259A_vector,
+    .shutdown = disable_8259A_vector,
+    .enable   = enable_8259A_vector,
+    .disable  = disable_8259A_vector,
+    .ack      = mask_and_ack_8259A_vector,
+    .end      = end_8259A_vector
 };
 
 /*
@@ -140,9 +145,9 @@ static struct hw_interrupt_type i8259A_irq_type = {
  */
 static unsigned int cached_irq_mask = 0xffff;
 
-#define __byte(x,y) 	(((unsigned char *)&(y))[x])
-#define cached_21	(__byte(0,cached_irq_mask))
-#define cached_A1	(__byte(1,cached_irq_mask))
+#define __byte(x,y) (((unsigned char *)&(y))[x])
+#define cached_21   (__byte(0,cached_irq_mask))
+#define cached_A1   (__byte(1,cached_irq_mask))
 
 /*
  * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
@@ -203,7 +208,6 @@ void make_8259A_irq(unsigned int irq)
 {
     disable_irq_nosync(irq);
     io_apic_irqs &= ~(1<<irq);
-    irq_desc[irq_to_vector(irq)].handler = &i8259A_irq_type;
     enable_irq(irq);
 }
 
@@ -219,14 +223,14 @@ static inline int i8259A_irq_real(unsigned int irq)
     int irqmask = 1<<irq;
 
     if (irq < 8) {
-        outb(0x0B,0x20);		/* ISR register */
+        outb(0x0B,0x20);                /* ISR register */
         value = inb(0x20) & irqmask;
-        outb(0x0A,0x20);		/* back to the IRR register */
+        outb(0x0A,0x20);                /* back to the IRR register */
         return value;
     }
-    outb(0x0B,0xA0);		/* ISR register */
+    outb(0x0B,0xA0);                    /* ISR register */
     value = inb(0xA0) & (irqmask >> 8);
-    outb(0x0A,0xA0);		/* back to the IRR register */
+    outb(0x0A,0xA0);                    /* back to the IRR register */
     return value;
 }
 
@@ -236,8 +240,9 @@ static inline int i8259A_irq_real(unsigned int irq)
  * first, _then_ send the EOI, and the order of EOI
  * to the two 8259s is important!
  */
-void mask_and_ack_8259A(unsigned int irq)
+static void mask_and_ack_8259A_vector(unsigned int vector)
 {
+    unsigned int irq = LEGACY_IRQ_FROM_VECTOR(vector);
     unsigned int irqmask = 1 << irq;
     unsigned long flags;
 
@@ -263,14 +268,14 @@ void mask_and_ack_8259A(unsigned int irq)
 
  handle_real_irq:
     if (irq & 8) {
-        inb(0xA1);		/* DUMMY - (do we need this?) */
+        inb(0xA1);              /* DUMMY - (do we need this?) */
         outb(cached_A1,0xA1);
         outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
-        outb(0x62,0x20);	/* 'Specific EOI' to master-IRQ2 */
+        outb(0x62,0x20);        /* 'Specific EOI' to master-IRQ2 */
     } else {
-        inb(0x21);		/* DUMMY - (do we need this?) */
+        inb(0x21);              /* DUMMY - (do we need this?) */
         outb(cached_21,0x21);
-        outb(0x60+irq,0x20);	/* 'Specific EOI' to master */
+        outb(0x60+irq,0x20);    /* 'Specific EOI' to master */
     }
     spin_unlock_irqrestore(&i8259A_lock, flags);
     return;
@@ -312,39 +317,39 @@ void __init init_8259A(int auto_eoi)
 
     spin_lock_irqsave(&i8259A_lock, flags);
 
-    outb(0xff, 0x21);	/* mask all of 8259A-1 */
-    outb(0xff, 0xA1);	/* mask all of 8259A-2 */
+    outb(0xff, 0x21);   /* mask all of 8259A-1 */
+    outb(0xff, 0xA1);   /* mask all of 8259A-2 */
 
     /*
      * outb_p - this has to work on a wide range of PC hardware.
      */
-    outb_p(0x11, 0x20);	/* ICW1: select 8259A-1 init */
-    outb_p(0x20 + 0, 0x21);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
-    outb_p(0x04, 0x21);	/* 8259A-1 (the master) has a slave on IR2 */
+    outb_p(0x11, 0x20);     /* ICW1: select 8259A-1 init */
+    outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
+    outb_p(0x04, 0x21);     /* 8259A-1 (the master) has a slave on IR2 */
     if (auto_eoi)
-        outb_p(0x03, 0x21);	/* master does Auto EOI */
+        outb_p(0x03, 0x21); /* master does Auto EOI */
     else
-        outb_p(0x01, 0x21);	/* master expects normal EOI */
+        outb_p(0x01, 0x21); /* master expects normal EOI */
 
-    outb_p(0x11, 0xA0);	/* ICW1: select 8259A-2 init */
-    outb_p(0x20 + 8, 0xA1);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
-    outb_p(0x02, 0xA1);	/* 8259A-2 is a slave on master's IR2 */
-    outb_p(0x01, 0xA1);	/* (slave's support for AEOI in flat mode
-                           is to be investigated) */
+    outb_p(0x11, 0xA0);     /* ICW1: select 8259A-2 init */
+    outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
+    outb_p(0x02, 0xA1);     /* 8259A-2 is a slave on master's IR2 */
+    outb_p(0x01, 0xA1);     /* (slave's support for AEOI in flat mode
+                               is to be investigated) */
 
     if (auto_eoi)
         /*
          * in AEOI mode we just have to mask the interrupt
          * when acking.
          */
-        i8259A_irq_type.ack = disable_8259A_irq;
+        i8259A_irq_type.ack = disable_8259A_vector;
     else
-        i8259A_irq_type.ack = mask_and_ack_8259A;
+        i8259A_irq_type.ack = mask_and_ack_8259A_vector;
 
-    udelay(100);		/* wait for 8259A to initialize */
+    udelay(100);            /* wait for 8259A to initialize */
 
-    outb(cached_21, 0x21);	/* restore master IRQ mask */
-    outb(cached_A1, 0xA1);	/* restore slave IRQ mask */
+    outb(cached_21, 0x21);  /* restore master IRQ mask */
+    outb(cached_A1, 0xA1);  /* restore slave IRQ mask */
 
     spin_unlock_irqrestore(&i8259A_lock, flags);
 }
@@ -397,9 +402,9 @@ void __init init_IRQ(void)
     /* Set the clock to HZ Hz */
 #define CLOCK_TICK_RATE 1193180 /* crystal freq (Hz) */
 #define LATCH (((CLOCK_TICK_RATE)+(HZ/2))/HZ)
-    outb_p(0x34,0x43);		/* binary, mode 2, LSB/MSB, ch 0 */
-    outb_p(LATCH & 0xff , 0x40);	/* LSB */
-    outb(LATCH >> 8 , 0x40);	/* MSB */
+    outb_p(0x34,0x43);           /* binary, mode 2, LSB/MSB, ch 0 */
+    outb_p(LATCH & 0xff , 0x40); /* LSB */
+    outb(LATCH >> 8 , 0x40);     /* MSB */
 
     setup_irq(2, &cascade);
 }

xen/arch/x86/irq.c

@@ -20,12 +20,12 @@ static void __do_IRQ_guest(int vector);
 
 void no_action(int cpl, void *dev_id, struct cpu_user_regs *regs) { }
 
-static void enable_none(unsigned int irq) { }
-static unsigned int startup_none(unsigned int irq) { return 0; }
-static void disable_none(unsigned int irq) { }
-static void ack_none(unsigned int irq)
+static void enable_none(unsigned int vector) { }
+static unsigned int startup_none(unsigned int vector) { return 0; }
+static void disable_none(unsigned int vector) { }
+static void ack_none(unsigned int vector)
 {
-    printk("Unexpected IRQ trap at vector %02x.\n", irq);
+    printk("Unexpected IRQ trap at vector %02x.\n", vector);
     ack_APIC_irq();
 }
 
@@ -55,7 +55,7 @@ inline void disable_irq_nosync(unsigned int irq)
     if ( desc->depth++ == 0 )
     {
         desc->status |= IRQ_DISABLED;
-        desc->handler->disable(irq);
+        desc->handler->disable(vector);
     }
 
     spin_unlock_irqrestore(&desc->lock, flags);
@@ -74,7 +74,7 @@ void enable_irq(unsigned int irq)
         desc->status &= ~IRQ_DISABLED;
         if ( (desc->status & (IRQ_PENDING | IRQ_REPLAY)) == IRQ_PENDING )
             desc->status |= IRQ_REPLAY;
-        desc->handler->enable(irq);
+        desc->handler->enable(vector);
     }
 
     spin_unlock_irqrestore(&desc->lock, flags);
@@ -83,14 +83,13 @@ void enable_irq(unsigned int irq)
 asmlinkage void do_IRQ(struct cpu_user_regs *regs)
 {
     unsigned int      vector = regs->entry_vector;
-    unsigned int      irq = vector_to_irq(vector);
     irq_desc_t       *desc = &irq_desc[vector];
     struct irqaction *action;
 
     perfc_incrc(irqs);
 
     spin_lock(&desc->lock);
-    desc->handler->ack(irq);
+    desc->handler->ack(vector);
 
     if ( likely(desc->status & IRQ_GUEST) )
     {
@@ -117,7 +116,7 @@ asmlinkage void do_IRQ(struct cpu_user_regs *regs)
         desc->status &= ~IRQ_PENDING;
         irq_enter(smp_processor_id());
         spin_unlock_irq(&desc->lock);
-        action->handler(irq, action->dev_id, regs);
+        action->handler(vector_to_irq(vector), action->dev_id, regs);
         spin_lock_irq(&desc->lock);
         irq_exit(smp_processor_id());
     }
@@ -125,7 +124,7 @@ asmlinkage void do_IRQ(struct cpu_user_regs *regs)
     desc->status &= ~IRQ_INPROGRESS;
 
  out:
-    desc->handler->end(irq);
+    desc->handler->end(vector);
     spin_unlock(&desc->lock);
 }
 
@@ -163,7 +162,7 @@ int setup_irq(unsigned int irq, struct irqaction *new)
     desc->action  = new;
     desc->depth   = 0;
     desc->status &= ~IRQ_DISABLED;
-    desc->handler->startup(irq);
+    desc->handler->startup(vector);
 
     spin_unlock_irqrestore(&desc->lock,flags);
 
@@ -220,7 +219,7 @@ int pirq_guest_unmask(struct domain *d)
             if ( !test_bit(d->pirq_to_evtchn[pirq], &s->evtchn_mask[0]) &&
                  test_and_clear_bit(pirq, &d->pirq_mask) &&
                  (--((irq_guest_action_t *)desc->action)->in_flight == 0) )
-                desc->handler->end(pirq);
+                desc->handler->end(irq_to_vector(pirq));
             spin_unlock_irq(&desc->lock);
         }
     }
@@ -273,12 +272,12 @@ int pirq_guest_bind(struct vcpu *v, int irq, int will_share)
         desc->depth = 0;
         desc->status |= IRQ_GUEST;
         desc->status &= ~IRQ_DISABLED;
-        desc->handler->startup(irq);
+        desc->handler->startup(vector);
 
         /* Attempt to bind the interrupt target to the correct CPU. */
         cpu_set(v->processor, cpumask);
         if ( desc->handler->set_affinity != NULL )
-            desc->handler->set_affinity(irq, cpumask);
+            desc->handler->set_affinity(vector, cpumask);
     }
     else if ( !will_share || !action->shareable )
     {
@@ -318,7 +317,7 @@ int pirq_guest_unbind(struct domain *d, int irq)
 
     if ( test_and_clear_bit(irq, &d->pirq_mask) &&
          (--action->in_flight == 0) )
-        desc->handler->end(irq);
+        desc->handler->end(vector);
 
     if ( action->nr_guests == 1 )
     {
@@ -327,7 +326,7 @@ int pirq_guest_unbind(struct domain *d, int irq)
         desc->depth   = 1;
         desc->status |= IRQ_DISABLED;
         desc->status &= ~IRQ_GUEST;
-        desc->handler->shutdown(irq);
+        desc->handler->shutdown(vector);
     }
     else
     {

xen/include/asm-x86/io_apic.h

@@ -14,44 +14,6 @@
 
 #ifdef CONFIG_X86_IO_APIC
 
-#ifdef CONFIG_PCI_MSI
-static inline int use_pci_vector(void)	{return 1;}
-static inline void disable_edge_ioapic_vector(unsigned int vector) { }
-static inline void end_edge_ioapic_vector (unsigned int vector) { }
-#define startup_level_ioapic	startup_level_ioapic_vector
-#define shutdown_level_ioapic	mask_IO_APIC_vector
-#define enable_level_ioapic	unmask_IO_APIC_vector
-#define disable_level_ioapic	mask_IO_APIC_vector
-#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_vector
-#define end_level_ioapic	end_level_ioapic_vector
-#define set_ioapic_affinity	set_ioapic_affinity_vector
-
-#define startup_edge_ioapic 	startup_edge_ioapic_vector
-#define shutdown_edge_ioapic 	disable_edge_ioapic_vector
-#define enable_edge_ioapic 	unmask_IO_APIC_vector
-#define disable_edge_ioapic 	disable_edge_ioapic_vector
-#define ack_edge_ioapic 	ack_edge_ioapic_vector
-#define end_edge_ioapic 	end_edge_ioapic_vector
-#else
-static inline int use_pci_vector(void)	{return 0;}
-static inline void disable_edge_ioapic_irq(unsigned int irq) { }
-static inline void end_edge_ioapic_irq (unsigned int irq) { }
-#define startup_level_ioapic	startup_level_ioapic_irq
-#define shutdown_level_ioapic	mask_IO_APIC_irq
-#define enable_level_ioapic	unmask_IO_APIC_irq
-#define disable_level_ioapic	mask_IO_APIC_irq
-#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_irq
-#define end_level_ioapic	end_level_ioapic_irq
-#define set_ioapic_affinity	set_ioapic_affinity_irq
-
-#define startup_edge_ioapic 	startup_edge_ioapic_irq
-#define shutdown_edge_ioapic 	disable_edge_ioapic_irq
-#define enable_edge_ioapic 	unmask_IO_APIC_irq
-#define disable_edge_ioapic 	disable_edge_ioapic_irq
-#define ack_edge_ioapic 	ack_edge_ioapic_irq
-#define end_edge_ioapic 	end_edge_ioapic_irq
-#endif
-
 #define IO_APIC_BASE(idx) \
 		((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
 		+ (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))

xen/include/asm-x86/irq.h

@@ -10,7 +10,10 @@
 
 #define IO_APIC_IRQ(irq)    (((irq) >= 16) || ((1<<(irq)) & io_apic_irqs))
 #define IO_APIC_VECTOR(irq) (irq_vector[irq])
-#define LEGACY_VECTOR(irq)  ((irq) + FIRST_EXTERNAL_VECTOR)
+
+#define LEGACY_VECTOR(irq)          ((irq) + FIRST_EXTERNAL_VECTOR)
+#define LEGACY_IRQ_FROM_VECTOR(vec) ((vec) - FIRST_EXTERNAL_VECTOR)
+
 #define irq_to_vector(irq)  \
     (IO_APIC_IRQ(irq) ? IO_APIC_VECTOR(irq) : LEGACY_VECTOR(irq))
 #define vector_to_irq(vec)  (vector_irq[vec])
@@ -29,13 +32,10 @@ void enable_8259A_irq(unsigned int irq);
 int i8259A_irq_pending(unsigned int irq);
 void make_8259A_irq(unsigned int irq);
 void init_8259A(int aeoi);
-void send_IPI_self(int vector);
-void init_VISWS_APIC_irqs(void);
+
 void setup_IO_APIC(void);
 void disable_IO_APIC(void);
 void print_IO_APIC(void);
-int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn);
-void send_IPI(int dest, int vector);
 void setup_ioapic_dest(void);
 
 extern unsigned long io_apic_irqs;