x86/Intel: add further support for Ivy Bridge CPU models

And some initial Haswell ones at once.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: "Nakajima, Jun" <jun.nakajima@intel.com>

xen/arch/x86/acpi/cpu_idle.c

@@ -128,11 +128,15 @@ static void do_get_hw_residencies(void *arg)
 
     switch ( c->x86_model )
     {
-    /* Ivy bridge */
-    case 0x3A:
     /* Sandy bridge */
     case 0x2A:
     case 0x2D:
+    /* Ivy bridge */
+    case 0x3A:
+    case 0x3E:
+    /* Haswell */
+    case 0x3c:
+    case 0x45:
         GET_PC2_RES(hw_res->pc2);
         GET_CC7_RES(hw_res->cc7);
         /* fall through */

xen/arch/x86/hvm/vmx/vmx.c

@@ -1746,7 +1746,9 @@ static const struct lbr_info *last_branch_msr_get(void)
         /* Sandy Bridge */
         case 42: case 45:
         /* Ivy Bridge */
-        case 58:
+        case 58: case 62:
+        /* Haswell */
+        case 60: case 69:
             return nh_lbr;
             break;
         /* Atom */

xen/arch/x86/hvm/vmx/vpmu_core2.c

@@ -747,6 +747,7 @@ int vmx_vpmu_initialise(struct vcpu *v, unsigned int vpmu_flags)
         case 46:
         case 47:
         case 58:
+        case 62:
             ret = core2_vpmu_initialise(v, vpmu_flags);
             if ( !ret )
                 vpmu->arch_vpmu_ops = &core2_vpmu_ops;