mirror of
https://github.com/xen-project/xen.git
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bitkeeper revision 1.1159.69.6 (4138ef8dDCN5JpkZV5nXmG3maQGSKw)
Merge ssh://scramble.cl.cam.ac.uk//usr/groups/xeno/BK/xeno.bk into camelot.eng.3leafnetworks.com:/home/kaf24/xeno
This commit is contained in:
commit
534ffcb416
11 files changed
+42
-208
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@@ -19,6 +19,7 @@ iap10@striker.cl.cam.ac.uk
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iap10@tetris.cl.cam.ac.uk
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jws22@gauntlet.cl.cam.ac.uk
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jws@cairnwell.research
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kaf24@camelot.eng.3leafnetworks.com
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kaf24@freefall.cl.cam.ac.uk
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kaf24@labyrinth.cl.cam.ac.uk
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kaf24@penguin.local
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@@ -134,7 +134,6 @@ static inline pte_t *pte_alloc_one(struct mm_struct *mm, unsigned long address)
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{
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clear_page(pte);
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__make_page_readonly(pte);
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queue_pte_pin(__pa(pte));
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}
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return pte;
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@@ -153,7 +152,6 @@ static inline pte_t *pte_alloc_one_fast(struct mm_struct *mm,
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static __inline__ void pte_free_slow(pte_t *pte)
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{
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queue_pte_unpin(__pa(pte));
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__make_page_writable(pte);
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free_page((unsigned long)pte);
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}
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@@ -85,8 +85,6 @@ static void DEBUG_disallow_pt_read(unsigned long va)
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#undef queue_invlpg
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#undef queue_pgd_pin
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#undef queue_pgd_unpin
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#undef queue_pte_pin
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#undef queue_pte_unpin
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#undef queue_set_ldt
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#endif
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@@ -219,7 +217,7 @@ void queue_pgd_pin(unsigned long ptr)
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spin_lock_irqsave(&update_lock, flags);
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update_queue[idx].ptr = phys_to_machine(ptr);
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update_queue[idx].ptr |= MMU_EXTENDED_COMMAND;
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update_queue[idx].val = MMUEXT_PIN_L2_TABLE;
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update_queue[idx].val = MMUEXT_PIN_TABLE;
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increment_index();
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spin_unlock_irqrestore(&update_lock, flags);
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}
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@@ -235,28 +233,6 @@ void queue_pgd_unpin(unsigned long ptr)
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spin_unlock_irqrestore(&update_lock, flags);
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}
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void queue_pte_pin(unsigned long ptr)
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{
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unsigned long flags;
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spin_lock_irqsave(&update_lock, flags);
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update_queue[idx].ptr = phys_to_machine(ptr);
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update_queue[idx].ptr |= MMU_EXTENDED_COMMAND;
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update_queue[idx].val = MMUEXT_PIN_L1_TABLE;
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increment_index();
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spin_unlock_irqrestore(&update_lock, flags);
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}
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void queue_pte_unpin(unsigned long ptr)
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{
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unsigned long flags;
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spin_lock_irqsave(&update_lock, flags);
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update_queue[idx].ptr = phys_to_machine(ptr);
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update_queue[idx].ptr |= MMU_EXTENDED_COMMAND;
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update_queue[idx].val = MMUEXT_UNPIN_TABLE;
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increment_index();
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spin_unlock_irqrestore(&update_lock, flags);
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}
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void queue_set_ldt(unsigned long ptr, unsigned long len)
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{
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unsigned long flags;
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@@ -339,7 +315,7 @@ void xen_pgd_pin(unsigned long ptr)
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spin_lock_irqsave(&update_lock, flags);
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update_queue[idx].ptr = phys_to_machine(ptr);
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update_queue[idx].ptr |= MMU_EXTENDED_COMMAND;
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update_queue[idx].val = MMUEXT_PIN_L2_TABLE;
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update_queue[idx].val = MMUEXT_PIN_TABLE;
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increment_index_and_flush();
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spin_unlock_irqrestore(&update_lock, flags);
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}
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@@ -355,28 +331,6 @@ void xen_pgd_unpin(unsigned long ptr)
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spin_unlock_irqrestore(&update_lock, flags);
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}
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void xen_pte_pin(unsigned long ptr)
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{
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unsigned long flags;
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spin_lock_irqsave(&update_lock, flags);
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update_queue[idx].ptr = phys_to_machine(ptr);
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update_queue[idx].ptr |= MMU_EXTENDED_COMMAND;
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update_queue[idx].val = MMUEXT_PIN_L1_TABLE;
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increment_index_and_flush();
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spin_unlock_irqrestore(&update_lock, flags);
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}
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void xen_pte_unpin(unsigned long ptr)
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{
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unsigned long flags;
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spin_lock_irqsave(&update_lock, flags);
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update_queue[idx].ptr = phys_to_machine(ptr);
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update_queue[idx].ptr |= MMU_EXTENDED_COMMAND;
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update_queue[idx].val = MMUEXT_UNPIN_TABLE;
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increment_index_and_flush();
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spin_unlock_irqrestore(&update_lock, flags);
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}
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void xen_set_ldt(unsigned long ptr, unsigned long len)
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{
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unsigned long flags;
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@@ -54,8 +54,6 @@ void queue_tlb_flush(void);
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void queue_invlpg(unsigned long ptr);
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void queue_pgd_pin(unsigned long ptr);
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void queue_pgd_unpin(unsigned long ptr);
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void queue_pte_pin(unsigned long ptr);
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void queue_pte_unpin(unsigned long ptr);
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void queue_set_ldt(unsigned long ptr, unsigned long bytes);
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void queue_machphys_update(unsigned long mfn, unsigned long pfn);
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void xen_l1_entry_update(pte_t *ptr, unsigned long val);
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@@ -65,8 +63,6 @@ void xen_tlb_flush(void);
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void xen_invlpg(unsigned long ptr);
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void xen_pgd_pin(unsigned long ptr);
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void xen_pgd_unpin(unsigned long ptr);
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void xen_pte_pin(unsigned long ptr);
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void xen_pte_unpin(unsigned long ptr);
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void xen_set_ldt(unsigned long ptr, unsigned long bytes);
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void xen_machphys_update(unsigned long mfn, unsigned long pfn);
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#define MMU_UPDATE_DEBUG 0
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@@ -141,14 +137,6 @@ extern page_update_debug_t update_debug_queue[];
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printk("PGD UNPIN %s %d: %08lx\n", __FILE__, __LINE__, (_p)); \
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queue_pgd_unpin(_p); \
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})
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#define queue_pte_pin(_p) ({ \
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printk("PTE PIN %s %d: %08lx\n", __FILE__, __LINE__, (_p)); \
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queue_pte_pin(_p); \
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})
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#define queue_pte_unpin(_p) ({ \
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printk("PTE UNPIN %s %d: %08lx\n", __FILE__, __LINE__, (_p)); \
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queue_pte_unpin(_p); \
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})
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#define queue_set_ldt(_p,_l) ({ \
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printk("SETL LDT %s %d: %08lx %d\n", __FILE__, __LINE__, (_p), (_l)); \
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queue_set_ldt((_p), (_l)); \
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@@ -270,7 +270,7 @@ static int setup_guestos(int xc_handle,
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* correct protection for the page
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*/
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if ( add_mmu_update(xc_handle, mmu,
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l2tab | MMU_EXTENDED_COMMAND, MMUEXT_PIN_L2_TABLE) )
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l2tab | MMU_EXTENDED_COMMAND, MMUEXT_PIN_TABLE) )
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goto error_out;
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start_info = map_pfn_writeable(
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@@ -473,28 +473,16 @@ int xc_linux_restore(int xc_handle, XcIOContext *ioctxt)
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*/
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for ( i = 0; i < nr_pfns; i++ )
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{
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if ( pfn_type[i] == (L1TAB|LPINTAB) )
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if ( pfn_type[i] != (L2TAB|LPINTAB) )
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continue;
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if ( add_mmu_update(xc_handle, mmu,
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(pfn_to_mfn_table[i]<<PAGE_SHIFT) |
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MMU_EXTENDED_COMMAND,
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MMUEXT_PIN_TABLE) )
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{
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if ( add_mmu_update(xc_handle, mmu,
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(pfn_to_mfn_table[i]<<PAGE_SHIFT) |
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MMU_EXTENDED_COMMAND,
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MMUEXT_PIN_L1_TABLE) ) {
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printf("ERR pin L1 pfn=%lx mfn=%lx\n",
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(unsigned long)i, pfn_to_mfn_table[i]);
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goto out;
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}
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}
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else if ( pfn_type[i] == (L2TAB|LPINTAB) )
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{
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if ( add_mmu_update(xc_handle, mmu,
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(pfn_to_mfn_table[i]<<PAGE_SHIFT) |
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MMU_EXTENDED_COMMAND,
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MMUEXT_PIN_L2_TABLE) )
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{
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printf("ERR pin L2 pfn=%lx mfn=%lx\n",
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(unsigned long)i, pfn_to_mfn_table[i]);
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goto out;
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}
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printf("ERR pin L2 pfn=%lx mfn=%lx\n",
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(unsigned long)i, pfn_to_mfn_table[i]);
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goto out;
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}
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}
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@@ -163,7 +163,7 @@ static int setup_guestos(int xc_handle,
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* correct protection for the page
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*/
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if ( add_mmu_update(xc_handle, mmu,
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l2tab | MMU_EXTENDED_COMMAND, MMUEXT_PIN_L2_TABLE) )
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l2tab | MMU_EXTENDED_COMMAND, MMUEXT_PIN_TABLE) )
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goto error_out;
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*virt_startinfo_addr =
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+18
-27
@@ -455,7 +455,8 @@ get_page_from_l1e(
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/* NB. Virtual address 'l2e' maps to a machine address within frame 'pfn'. */
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static int
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get_page_from_l2e(
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l2_pgentry_t l2e, unsigned long pfn, struct domain *d, unsigned long va_idx)
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l2_pgentry_t l2e, unsigned long pfn,
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struct domain *d, unsigned long va_idx)
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{
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int rc;
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@@ -471,7 +472,7 @@ get_page_from_l2e(
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rc = get_page_and_type_from_pagenr(
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l2_pgentry_to_pagenr(l2e),
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PGT_l1_page_table | (va_idx<<PGT_va_shift), d);
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PGT_l1_page_table | (va_idx<<PGT_va_shift), d);
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if ( unlikely(!rc) )
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return get_linear_pagetable(l2e, pfn, d);
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@@ -671,8 +672,8 @@ static int mod_l2_entry(l2_pgentry_t *pl2e,
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return update_l2e(pl2e, ol2e, nl2e);
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if ( unlikely(!get_page_from_l2e(nl2e, pfn, current,
|
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((unsigned long)
|
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pl2e & ~PAGE_MASK) >> 2 )) )
|
||||
((unsigned long)pl2e &
|
||||
~PAGE_MASK) >> 2)) )
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||||
return 0;
|
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|
||||
if ( unlikely(!update_l2e(pl2e, ol2e, nl2e)) )
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||||
@@ -826,21 +827,9 @@ static int do_extended_command(unsigned long ptr, unsigned long val)
|
||||
|
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switch ( cmd )
|
||||
{
|
||||
case MMUEXT_PIN_L1_TABLE:
|
||||
case MMUEXT_PIN_L2_TABLE:
|
||||
|
||||
/* When we pin an L1 page we now insist that the va
|
||||
backpointer (used for writable page tables) must still be
|
||||
mutable. This is an additional restriction even for guests
|
||||
that don't use writable page tables, but I don't think it
|
||||
will break anything as guests typically pin pages before
|
||||
they are used, hence they'll still be mutable. */
|
||||
|
||||
case MMUEXT_PIN_TABLE:
|
||||
okay = get_page_and_type_from_pagenr(
|
||||
pfn,
|
||||
((cmd==MMUEXT_PIN_L2_TABLE) ?
|
||||
PGT_l2_page_table : (PGT_l1_page_table | PGT_va_mutable) ) ,
|
||||
FOREIGNDOM);
|
||||
pfn, PGT_l2_page_table, FOREIGNDOM);
|
||||
|
||||
if ( unlikely(!okay) )
|
||||
{
|
||||
@@ -1183,6 +1172,7 @@ int do_mmu_update(mmu_update_t *ureqs, int count, int *success_count)
|
||||
unsigned long prev_spfn = 0;
|
||||
l1_pgentry_t *prev_spl1e = 0;
|
||||
struct domain *d = current;
|
||||
u32 type_info;
|
||||
|
||||
perfc_incrc(calls_to_mmu_update);
|
||||
perfc_addc(num_page_updates, count);
|
||||
@@ -1231,10 +1221,11 @@ int do_mmu_update(mmu_update_t *ureqs, int count, int *success_count)
|
||||
}
|
||||
|
||||
page = &frame_table[pfn];
|
||||
switch ( (page->u.inuse.type_info & PGT_type_mask) )
|
||||
switch ( (type_info = page->u.inuse.type_info) & PGT_type_mask )
|
||||
{
|
||||
case PGT_l1_page_table:
|
||||
if ( likely(passive_get_page_type(page, PGT_l1_page_table)) )
|
||||
if ( likely(get_page_type(
|
||||
page, type_info & (PGT_type_mask|PGT_va_mask))) )
|
||||
{
|
||||
okay = mod_l1_entry((l1_pgentry_t *)va,
|
||||
mk_l1_pgentry(req.val));
|
||||
@@ -1484,11 +1475,11 @@ void ptwr_reconnect_disconnected(unsigned long addr)
|
||||
[ptwr_info[cpu].writable_l1>>PAGE_SHIFT];
|
||||
|
||||
#ifdef PTWR_TRACK_DOMAIN
|
||||
if (ptwr_domain[cpu] != get_current()->domain)
|
||||
if (ptwr_domain[cpu] != current->domain)
|
||||
printk("ptwr_reconnect_disconnected domain mismatch %d != %d\n",
|
||||
ptwr_domain[cpu], get_current()->domain);
|
||||
ptwr_domain[cpu], current->domain);
|
||||
#endif
|
||||
PTWR_PRINTK(("[A] page fault in disconnected space: addr %08lx space %08lx\n",
|
||||
PTWR_PRINTK(("[A] page fault in disconn space: addr %08lx space %08lx\n",
|
||||
addr, ptwr_info[cpu].disconnected << L2_PAGETABLE_SHIFT));
|
||||
pl2e = &linear_l2_table[ptwr_info[cpu].disconnected];
|
||||
|
||||
@@ -1560,9 +1551,9 @@ void ptwr_flush_inactive(void)
|
||||
int i, idx;
|
||||
|
||||
#ifdef PTWR_TRACK_DOMAIN
|
||||
if (ptwr_info[cpu].domain != get_current()->domain)
|
||||
if (ptwr_info[cpu].domain != current->domain)
|
||||
printk("ptwr_flush_inactive domain mismatch %d != %d\n",
|
||||
ptwr_info[cpu].domain, get_current()->domain);
|
||||
ptwr_info[cpu].domain, current->domain);
|
||||
#endif
|
||||
#if 0
|
||||
{
|
||||
@@ -1643,9 +1634,9 @@ int ptwr_do_page_fault(unsigned long addr)
|
||||
if ( (page->u.inuse.type_info & PGT_type_mask) == PGT_l1_page_table )
|
||||
{
|
||||
#ifdef PTWR_TRACK_DOMAIN
|
||||
if ( ptwr_info[cpu].domain != get_current()->domain )
|
||||
if ( ptwr_info[cpu].domain != current->domain )
|
||||
printk("ptwr_do_page_fault domain mismatch %d != %d\n",
|
||||
ptwr_info[cpu].domain, get_current()->domain);
|
||||
ptwr_info[cpu].domain, current->domain);
|
||||
#endif
|
||||
pl2e = &linear_l2_table[(page->u.inuse.type_info &
|
||||
PGT_va_mask) >> PGT_va_shift];
|
||||
|
||||
@@ -374,20 +374,6 @@ void __enter_scheduler(void)
|
||||
cleanup_writable_pagetable(
|
||||
prev, PTWR_CLEANUP_ACTIVE | PTWR_CLEANUP_INACTIVE);
|
||||
|
||||
#ifdef PTWR_TRACK_DOMAIN
|
||||
{
|
||||
extern domid_t ptwr_domain[];
|
||||
int cpu = smp_processor_id();
|
||||
if (ptwr_domain[cpu] != prev->domain)
|
||||
printk("switch_to domain mismatch %d != %d\n",
|
||||
ptwr_domain[cpu], prev->domain);
|
||||
ptwr_domain[cpu] = next->domain;
|
||||
if (ptwr_disconnected[cpu] != ENTRIES_PER_L2_PAGETABLE ||
|
||||
ptwr_writable_idx[cpu])
|
||||
printk("switch_to ptwr dirty!!!\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
perfc_incrc(sched_ctx);
|
||||
|
||||
#if defined(WAKE_HISTO)
|
||||
|
||||
@@ -71,10 +71,9 @@ struct pfn_info
|
||||
/* Has this page been validated for use as its current type? */
|
||||
#define _PGT_validated 28
|
||||
#define PGT_validated (1<<_PGT_validated)
|
||||
/* 10-bit most significant bits of va address if used as l1 page table */
|
||||
/* The 10 most significant bits of virt address if this is a L1 page table. */
|
||||
#define PGT_va_shift 18
|
||||
#define PGT_va_mask (((1<<10)-1)<<PGT_va_shift)
|
||||
#define PGT_va_mutable PGT_va_mask /* va backpointer is still mutable */
|
||||
/* 18-bit count of uses of this frame as its current type. */
|
||||
#define PGT_count_mask ((1<<18)-1)
|
||||
|
||||
@@ -199,13 +198,6 @@ static inline void put_page_type(struct pfn_info *page)
|
||||
nx &= ~PGT_validated;
|
||||
}
|
||||
}
|
||||
else if ( unlikely( ((nx & PGT_count_mask) == 1) &&
|
||||
test_bit(_PGC_guest_pinned, &page->count_info)) )
|
||||
{
|
||||
/* if the page is pinned, but we're dropping the last reference
|
||||
then make the va backpointer mutable again */
|
||||
nx |= PGT_va_mutable;
|
||||
}
|
||||
}
|
||||
while ( unlikely((y = cmpxchg(&page->u.inuse.type_info, x, nx)) != x) );
|
||||
}
|
||||
@@ -230,27 +222,15 @@ static inline int get_page_type(struct pfn_info *page, u32 type)
|
||||
nx &= ~(PGT_type_mask | PGT_va_mask | PGT_validated);
|
||||
nx |= type;
|
||||
/* No extra validation needed for writable pages. */
|
||||
if ( (type & PGT_type_mask) == PGT_writable_page )
|
||||
if ( type == PGT_writable_page )
|
||||
nx |= PGT_validated;
|
||||
}
|
||||
}
|
||||
else if ( unlikely((x & PGT_type_mask) != (type & PGT_type_mask) ) )
|
||||
else if ( unlikely((x & (PGT_type_mask|PGT_va_mask)) != type) )
|
||||
{
|
||||
DPRINTK("Unexpected type (saw %08x != exp %08x) for pfn %08lx\n",
|
||||
x & PGT_type_mask, type, page_to_pfn(page));
|
||||
return 0;
|
||||
}
|
||||
else if ( (x & PGT_va_mask) == PGT_va_mutable )
|
||||
{
|
||||
/* The va_backpointer is currently mutable, hence we update it. */
|
||||
nx &= ~PGT_va_mask;
|
||||
nx |= type; /* we know the actual type is correct */
|
||||
}
|
||||
else if ( unlikely((x & PGT_va_mask) != (type & PGT_va_mask) ) )
|
||||
{
|
||||
/* The va backpointer wasn't mutable, and is different :-( */
|
||||
DPRINTK("Unexpected va backpointer (saw %08x != exp %08x) for pfn %08lx\n",
|
||||
x, type, page_to_pfn(page));
|
||||
DPRINTK("Unexpected type or va backptr (saw %08x != exp %08x) "
|
||||
"for pfn %08lx\n",
|
||||
x & (PGT_type_mask|PGT_va_mask), type, page_to_pfn(page));
|
||||
return 0;
|
||||
}
|
||||
else if ( unlikely(!(x & PGT_validated)) )
|
||||
@@ -286,55 +266,6 @@ static inline int get_page_type(struct pfn_info *page, u32 type)
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* This 'passive' version of get_page_type doesn't attempt to validate
|
||||
the page, but just checks the type and increments the type count. The
|
||||
function is called while doing a NORMAL_PT_UPDATE of an entry in an L1
|
||||
page table: We want to 'lock' the page for the brief beriod while
|
||||
we're doing the update, but we're not actually linking it in to a
|
||||
pagetable. */
|
||||
|
||||
static inline int passive_get_page_type(struct pfn_info *page, u32 type)
|
||||
{
|
||||
u32 nx, x, y = page->u.inuse.type_info;
|
||||
again:
|
||||
do {
|
||||
x = y;
|
||||
nx = x + 1;
|
||||
if ( unlikely((nx & PGT_count_mask) == 0) )
|
||||
{
|
||||
DPRINTK("Type count overflow on pfn %08lx\n", page_to_pfn(page));
|
||||
return 0;
|
||||
}
|
||||
else if ( unlikely((x & PGT_count_mask) == 0) )
|
||||
{
|
||||
if ( (x & (PGT_type_mask|PGT_va_mask)) != type )
|
||||
{
|
||||
nx &= ~(PGT_type_mask | PGT_va_mask | PGT_validated);
|
||||
nx |= type;
|
||||
}
|
||||
}
|
||||
else if ( unlikely((x & PGT_type_mask) != (type & PGT_type_mask) ) )
|
||||
{
|
||||
DPRINTK("Unexpected type (saw %08x != exp %08x) for pfn %08lx\n",
|
||||
x & PGT_type_mask, type, page_to_pfn(page));
|
||||
return 0;
|
||||
}
|
||||
else if ( unlikely(!(x & PGT_validated)) )
|
||||
{
|
||||
/* Someone else is updating validation of this page. Wait... */
|
||||
while ( (y = page->u.inuse.type_info) != x )
|
||||
{
|
||||
rep_nop();
|
||||
barrier();
|
||||
}
|
||||
goto again;
|
||||
}
|
||||
}
|
||||
while ( unlikely((y = cmpxchg(&page->u.inuse.type_info, x, nx)) != x) );
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
static inline void put_page_and_type(struct pfn_info *page)
|
||||
{
|
||||
|
||||
@@ -104,9 +104,9 @@
|
||||
* ptr[1:0] == MMU_EXTENDED_COMMAND:
|
||||
* val[7:0] -- MMUEXT_* command.
|
||||
*
|
||||
* val[7:0] == MMUEXT_(UN)PIN_*_TABLE:
|
||||
* ptr[:2] -- Machine address of frame to be (un)pinned as a p.t. page.
|
||||
* The frame must belong to the FD, if one is specified.
|
||||
* val[7:0] == MMUEXT_[UN]PIN_TABLE:
|
||||
* ptr[:2] -- Machine address of frame to be (un)pinned as a top-level p.t.
|
||||
* page. The frame must belong to the FD, if one is specified.
|
||||
*
|
||||
* val[7:0] == MMUEXT_NEW_BASEPTR:
|
||||
* ptr[:2] -- Machine address of new page-table base to install in MMU.
|
||||
@@ -142,10 +142,7 @@
|
||||
#define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */
|
||||
#define MMU_MACHPHYS_UPDATE 2 /* ptr = MA of frame to modify entry for */
|
||||
#define MMU_EXTENDED_COMMAND 3 /* least 8 bits of val demux further */
|
||||
#define MMUEXT_PIN_L1_TABLE 0 /* ptr = MA of frame to pin */
|
||||
#define MMUEXT_PIN_L2_TABLE 1 /* ptr = MA of frame to pin */
|
||||
#define MMUEXT_PIN_L3_TABLE 2 /* ptr = MA of frame to pin */
|
||||
#define MMUEXT_PIN_L4_TABLE 3 /* ptr = MA of frame to pin */
|
||||
#define MMUEXT_PIN_TABLE 0 /* ptr = MA of frame to pin */
|
||||
#define MMUEXT_UNPIN_TABLE 4 /* ptr = MA of frame to unpin */
|
||||
#define MMUEXT_NEW_BASEPTR 5 /* ptr = MA of new pagetable base */
|
||||
#define MMUEXT_TLB_FLUSH 6 /* ptr = NULL */
|
||||
|
||||