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xen/arm: vgic: Rename emulate_sysreg callback to emulate_reg
We will want to emulate co-processor registers access in a follow-up patch. Signed-off-by: Julien Grall <julien.grall@arm.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
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@@ -1328,6 +1328,17 @@ static bool vgic_v3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr)
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}
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}
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static bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr)
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{
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switch (hsr.ec)
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{
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case HSR_EC_SYSREG:
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return vgic_v3_emulate_sysreg(regs, hsr);
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default:
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return false;
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}
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}
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static const struct mmio_handler_ops vgic_rdistr_mmio_handler = {
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.read = vgic_v3_rdistr_mmio_read,
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.write = vgic_v3_rdistr_mmio_write,
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@@ -1491,7 +1502,7 @@ static const struct vgic_ops v3_ops = {
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.vcpu_init = vgic_v3_vcpu_init,
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.domain_init = vgic_v3_domain_init,
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.domain_free = vgic_v3_domain_free,
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.emulate_sysreg = vgic_v3_emulate_sysreg,
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.emulate_reg = vgic_v3_emulate_reg,
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/*
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* We use both AFF1 and AFF0 in (v)MPIDR. Thus, the max number of CPU
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* that can be supported is up to 4096(==256*16) in theory.
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+2
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@@ -550,9 +550,9 @@ bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
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{
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struct vcpu *v = current;
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ASSERT(v->domain->arch.vgic.handler->emulate_sysreg != NULL);
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ASSERT(v->domain->arch.vgic.handler->emulate_reg != NULL);
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return v->domain->arch.vgic.handler->emulate_sysreg(regs, hsr);
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return v->domain->arch.vgic.handler->emulate_reg(regs, hsr);
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}
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bool vgic_reserve_virq(struct domain *d, unsigned int virq)
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@@ -130,8 +130,8 @@ struct vgic_ops {
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int (*domain_init)(struct domain *d);
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/* Release resources that were allocated by domain_init */
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void (*domain_free)(struct domain *d);
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/* vGIC sysreg emulation */
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bool (*emulate_sysreg)(struct cpu_user_regs *regs, union hsr hsr);
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/* vGIC sysreg/cpregs emulate */
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bool (*emulate_reg)(struct cpu_user_regs *regs, union hsr hsr);
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/* Maximum number of vCPU supported */
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const unsigned int max_vcpus;
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};
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