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xen: arm: Annotate registers trapped by MDCR_EL2.TDOSA
Gather the affected handlers in a single place per trap type. Add some HSR_SYSREG and AArch32 defines for those registers (because I'd already typed them in when I realised I didn't need them). Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Reviewed-by: Julien Grall <julien.grall@citrix.com>
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@@ -1817,6 +1817,21 @@ static void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr)
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switch ( hsr.bits & HSR_CP32_REGS_MASK )
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{
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/*
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* MDCR_EL2.TDOSA
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*
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* ARMv7 (DDI 0406C.b): B1.14.15
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* ARMv8 (DDI 0487A.d): D1-1509 Table D1-58
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*
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* Unhandled:
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* DBGOSLSR
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* DBGPRCR
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*/
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case HSR_CPREG32(DBGOSLAR):
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return handle_wo_wi(regs, r, cp32.read, hsr, 1);
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case HSR_CPREG32(DBGOSDLR):
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return handle_raz_wi(regs, r, cp32.read, hsr, 1);
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case HSR_CPREG32(DBGDIDR):
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/*
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* Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis
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@@ -1856,12 +1871,8 @@ static void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr)
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case HSR_CPREG32(DBGWCR0):
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case HSR_CPREG32(DBGBVR1):
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case HSR_CPREG32(DBGBCR1):
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case HSR_CPREG32(DBGOSDLR):
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return handle_raz_wi(regs, r, cp32.read, hsr, 1);
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case HSR_CPREG32(DBGOSLAR):
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return handle_wo_wi(regs, r, cp32.read, hsr, 1);
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/*
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* CPTR_EL2.TTA
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*
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@@ -1943,6 +1954,18 @@ static void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr)
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return;
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}
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/*
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* MDCR_EL2.TDOSA
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*
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* ARMv7 (DDI 0406C.b): B1.14.15
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* ARMv8 (DDI 0487A.d): D1-1509 Table D1-58
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*
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* Unhandled:
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* DBGDTRTXint
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* DBGDTRRXint
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*
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* And all other unknown registers.
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*/
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gdprintk(XENLOG_ERR,
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"%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n",
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cp64.read ? "mrrc" : "mcrr",
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@@ -1997,6 +2020,20 @@ static void do_sysreg(struct cpu_user_regs *regs,
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case HSR_SYSREG_MDRAR_EL1:
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return handle_ro_raz(regs, x, hsr.sysreg.read, hsr, 1);
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/*
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* MDCR_EL2.TDOSA
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*
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* ARMv8 (DDI 0487A.d): D1-1509 Table D1-58
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*
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* Unhandled:
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* OSLSR_EL1
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* DBGPRCR_EL1
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*/
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case HSR_SYSREG_OSLAR_EL1:
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return handle_wo_wi(regs, x, hsr.sysreg.read, hsr, 1);
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case HSR_SYSREG_OSDLR_EL1:
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return handle_raz_wi(regs, x, hsr.sysreg.read, hsr, 1);
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/* RAZ/WI registers: */
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/* - Debug */
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case HSR_SYSREG_MDSCR_EL1:
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@@ -2006,8 +2043,6 @@ static void do_sysreg(struct cpu_user_regs *regs,
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/* - Watchpoints */
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HSR_SYSREG_DBG_CASES(DBGWVR):
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HSR_SYSREG_DBG_CASES(DBGWCR):
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/* - Double Lock Register */
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case HSR_SYSREG_OSDLR_EL1:
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/* - Perf monitors */
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case HSR_SYSREG_PMINTENSET_EL1:
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case HSR_SYSREG_PMINTENCLR_EL1:
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@@ -2049,10 +2084,6 @@ static void do_sysreg(struct cpu_user_regs *regs,
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*/
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return handle_raz_wi(regs, x, hsr.sysreg.read, hsr, 1);
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/* Write only, Write ignore registers: */
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case HSR_SYSREG_OSLAR_EL1:
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return handle_wo_wi(regs, x, hsr.sysreg.read, hsr, 1);
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case HSR_SYSREG_CNTP_CTL_EL0:
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case HSR_SYSREG_CNTP_TVAL_EL0:
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case HSR_SYSREG_CNTP_CVAL_EL0:
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@@ -83,7 +83,9 @@
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#define DBGBVR1 p14,0,c0,c1,4 /* Breakpoint Value 1 */
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#define DBGBCR1 p14,0,c0,c1,5 /* Breakpoint Control 1 */
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#define DBGOSLAR p14,0,c1,c0,4 /* OS Lock Access */
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#define DBGOSLSR p14,0,c1,c1,4 /* OS Lock Status Register */
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#define DBGOSDLR p14,0,c1,c3,4 /* OS Double Lock */
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#define DBGPRCR p14,0,c1,c4,4 /* Debug Power Control Register */
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/* CP14 CR0: */
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#define TEECR p14,6,c0,c0,0 /* ThumbEE Configuration Register */
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@@ -47,7 +47,9 @@
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#define HSR_SYSREG_MDSCR_EL1 HSR_SYSREG(2,0,c0,c2,2)
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#define HSR_SYSREG_MDRAR_EL1 HSR_SYSREG(2,0,c1,c0,0)
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#define HSR_SYSREG_OSLAR_EL1 HSR_SYSREG(2,0,c1,c0,4)
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#define HSR_SYSREG_OSLSR_EL1 HSR_SYSREG(2,0,c1,c1,4)
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#define HSR_SYSREG_OSDLR_EL1 HSR_SYSREG(2,0,c1,c3,4)
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#define HSR_SYSREG_DBGPRCR_EL1 HSR_SYSREG(2,0,c1,c4,4)
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#define HSR_SYSREG_MDCCSR_EL0 HSR_SYSREG(2,3,c0,c1,0)
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#define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4)
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