mirror of
https://github.com/xen-project/xen.git
synced 2026-10-29 18:50:05 +01:00
x86: fix logical ANDs used to mask bitfields.
Signed-off-by: Tim Deegan <tim@xen.org> Acked-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> Committed-by: Tim Deegan <tim@xen.org>
This commit is contained in:
1 parent
b656ffb608
commit
5a90fc8ea3
2 files changed
+3
-3
No files matched your search
@@ -752,7 +752,7 @@ static void svm_lwp_interrupt(struct cpu_user_regs *regs)
|
||||
ack_APIC_irq();
|
||||
vlapic_set_irq(
|
||||
vcpu_vlapic(curr),
|
||||
(curr->arch.hvm_svm.guest_lwp_cfg >> 40) && 0xff,
|
||||
(curr->arch.hvm_svm.guest_lwp_cfg >> 40) & 0xff,
|
||||
0);
|
||||
}
|
||||
|
||||
|
||||
@@ -1382,7 +1382,7 @@ void vmx_inject_extint(int trap)
|
||||
if ( nestedhvm_vcpu_in_guestmode(v) ) {
|
||||
pin_based_cntrl = __get_vvmcs(vcpu_nestedhvm(v).nv_vvmcx,
|
||||
PIN_BASED_VM_EXEC_CONTROL);
|
||||
if ( pin_based_cntrl && PIN_BASED_EXT_INTR_MASK ) {
|
||||
if ( pin_based_cntrl & PIN_BASED_EXT_INTR_MASK ) {
|
||||
nvmx_enqueue_n2_exceptions (v,
|
||||
INTR_INFO_VALID_MASK | (X86_EVENTTYPE_EXT_INTR<<8) | trap,
|
||||
HVM_DELIVER_NO_ERROR_CODE);
|
||||
@@ -1401,7 +1401,7 @@ void vmx_inject_nmi(void)
|
||||
if ( nestedhvm_vcpu_in_guestmode(v) ) {
|
||||
pin_based_cntrl = __get_vvmcs(vcpu_nestedhvm(v).nv_vvmcx,
|
||||
PIN_BASED_VM_EXEC_CONTROL);
|
||||
if ( pin_based_cntrl && PIN_BASED_NMI_EXITING ) {
|
||||
if ( pin_based_cntrl & PIN_BASED_NMI_EXITING ) {
|
||||
nvmx_enqueue_n2_exceptions (v,
|
||||
INTR_INFO_VALID_MASK | (X86_EVENTTYPE_NMI<<8) | TRAP_nmi,
|
||||
HVM_DELIVER_NO_ERROR_CODE);
|
||||
|
||||