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x86emul: support AVX512{BW,DQ} mask move insns
Entries to the tables in evex-disp8.c are added despite these insns not allowing for memory operands, with the goal of the tables giving a complete picture of the supported EVEX-encoded insns in the end. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
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@@ -314,9 +314,12 @@ static const struct test avx512bw_all[] = {
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INSN(pminsw, 66, 0f, ea, vl, w, vl),
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INSN(pminub, 66, 0f, da, vl, b, vl),
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INSN(pminuw, 66, 0f38, 3a, vl, w, vl),
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// pmovb2m, f3, 0f38, 29, b
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// pmovm2, f3, 0f38, 28, bw
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INSN(pmovswb, f3, 0f38, 20, vl_2, b, vl),
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INSN(pmovsxbw, 66, 0f38, 20, vl_2, b, vl),
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INSN(pmovuswb, f3, 0f38, 10, vl_2, b, vl),
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// pmovw2m, f3, 0f38, 29, w
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INSN(pmovwb, f3, 0f38, 30, vl_2, b, vl),
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INSN(pmovzxbw, 66, 0f38, 30, vl_2, b, vl),
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INSN(pmulhuw, 66, 0f, e4, vl, w, vl),
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@@ -364,6 +367,9 @@ static const struct test avx512dq_all[] = {
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INSN_PFP(andn, 0f, 55),
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INSN(broadcasti32x2, 66, 0f38, 59, el_2, d, vl),
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INSN_PFP(or, 0f, 56),
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// pmovd2m, f3, 0f38, 39, d
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// pmovm2, f3, 0f38, 38, dq
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// pmovq2m, f3, 0f38, 39, q
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INSN(pmullq, 66, 0f38, 40, vl, q, vl),
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INSN_PFP(xor, 0f, 57),
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};
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@@ -12,17 +12,23 @@
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#if SIZE == 1
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# define _(x) x##b
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# define _v(x, t) _v_(x##q, t)
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#elif SIZE == 2
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# define _(x) x##w
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# define _v(x, t) _v_(x##d, t)
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# define WIDEN(x) x##bw
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#elif SIZE == 4
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# define _(x) x##d
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# define _v(x, t) _v_(x##w, t)
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# define WIDEN(x) x##wd
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#elif SIZE == 8
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# define _(x) x##q
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# define _v(x, t) _v_(x##b, t)
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# define WIDEN(x) x##dq
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#endif
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#define _v_(x, t) v##x##t
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.macro check res1:req, res2:req, line:req
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_(kmov) %\res1, DATA(out)
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#if SIZE < 8 || !defined(__i386__)
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@@ -129,6 +135,15 @@ _start:
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ret
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1:
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#endif
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#if SIZE > 2 ? defined(__AVX512BW__) : defined(__AVX512DQ__)
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_(kmov) DATA(in1), %k0
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_v(pmovm2,) %k0, %zmm7
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_v(pmov,2m) %zmm7, %k3
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check k0, k3, __LINE__
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#endif
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xor %eax, %eax
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@@ -8441,6 +8441,21 @@ x86_emulate(
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elem_bytes = (b & 7) < 3 ? 1 : (b & 7) != 5 ? 2 : 4;
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goto avx512f_no_sae;
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case X86EMUL_OPC_EVEX_F3(0x0f38, 0x29): /* vpmov{b,w}2m [xyz]mm,k */
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case X86EMUL_OPC_EVEX_F3(0x0f38, 0x39): /* vpmov{d,q}2m [xyz]mm,k */
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generate_exception_if(!evex.r || !evex.R, EXC_UD);
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/* fall through */
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case X86EMUL_OPC_EVEX_F3(0x0f38, 0x28): /* vpmovm2{b,w} k,[xyz]mm */
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case X86EMUL_OPC_EVEX_F3(0x0f38, 0x38): /* vpmovm2{d,q} k,[xyz]mm */
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if ( b & 0x10 )
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host_and_vcpu_must_have(avx512dq);
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else
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host_and_vcpu_must_have(avx512bw);
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generate_exception_if(evex.opmsk || ea.type != OP_REG, EXC_UD);
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d |= TwoOp;
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op_bytes = 16 << evex.lr;
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goto avx512f_no_sae;
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case X86EMUL_OPC_66(0x0f38, 0x2a): /* movntdqa m128,xmm */
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case X86EMUL_OPC_VEX_66(0x0f38, 0x2a): /* vmovntdqa mem,{x,y}mm */
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generate_exception_if(ea.type != OP_MEM, EXC_UD);
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