xen/arm: Fix guest secondaries CPU boot after bcac10f

The commit bcac10f "xen: arm: support building a 64-bit dom0 domain" breaks
secondary cpus boot for all the guest. Linux requires CPUs to boot on SVC mode.

Divide PSR_GUEST_INIT in 2 distinct defines: one for 32 bit, the other for 64
bits guests.

Signed-off-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>

xen/arch/arm/domain_build.c

@@ -597,7 +597,7 @@ int construct_dom0(struct domain *d)
 
     if ( is_pv32_domain(d) )
     {
-        regs->cpsr = PSR_GUEST_INIT|PSR_MODE_SVC;
+        regs->cpsr = PSR_GUEST32_INIT;
 
         /* Pretend to be a Cortex A15 */
         d->arch.vpidr = 0x410fc0f0;
@@ -619,7 +619,7 @@ int construct_dom0(struct domain *d)
 #ifdef CONFIG_ARM_64
     else
     {
-        regs->cpsr = PSR_GUEST_INIT|PSR_MODE_EL1h;
+        regs->cpsr = PSR_GUEST64_INIT;
         /* From linux/Documentation/arm64/booting.txt */
         regs->x0 = kinfo.dtb_paddr;
         regs->x1 = 0; /* Reserved for future use */

xen/arch/arm/psci.c

@@ -47,7 +47,13 @@ int do_psci_cpu_on(uint32_t vcpuid, register_t entry_point)
     ctxt->ttbr0 = 0;
     ctxt->ttbr1 = 0;
     ctxt->ttbcr = 0; /* Defined Reset Value */
-    ctxt->user_regs.cpsr = PSR_GUEST_INIT;
+    if ( is_pv32_domain(d) )
+        ctxt->user_regs.cpsr = PSR_GUEST32_INIT;
+#ifdef CONFIG_ARM_64
+    else
+        ctxt->user_regs.cpsr = PSR_GUEST64_INIT;
+#endif
+
     /* Start the VCPU with THUMB set if it's requested by the kernel */
     if ( is_thumb )
         ctxt->user_regs.cpsr |= PSR_THUMB;

xen/include/asm-arm/processor.h

@@ -47,7 +47,11 @@
 #define SCTLR_BASE        0x00c50078
 #define HSCTLR_BASE       0x30c51878
 
-#define PSR_GUEST_INIT  (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK)
+#define PSR_GUEST32_INIT  (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC)
+
+#ifdef CONFIG_ARM_64
+#define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h)
+#endif
 
 /* HCR Hyp Configuration Register */
 #define HCR_RW          (1<<31) /* Register Width, ARM64 only */