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x86-64: extend manageable memory range to 5Tb

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Extend the virtual range reserved for the 1:1 mapping to cover 5Tb,
and make the virtual size of the frame table gets match whatever the
1:1 table can cover.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
This commit is contained in:
Keir Fraser committed 2009-09-22 08:14:48 +01:00
1 parent d189c54b3d
commit 615588563e
5 files changed
+34 -22
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xen/arch/x86/boot/head.S
+4 -4
View File
@@ -33,7 +33,7 @@ ENTRY(start)
/* Checksum: must be the negated sum of the first two fields. */
.long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)
.section .init.text
.section .init.text, "ax"
.Lbad_cpu_msg: .asciz "ERR: Not a 64-bit CPU!"
.Lbad_ldr_msg: .asciz "ERR: Not a Multiboot bootloader!"
@@ -128,13 +128,13 @@ __start:
loop 1b
/* Initialise L3 xen-map page directory entry. */
mov $(sym_phys(l2_xenmap)+7),%eax
mov %eax,sym_phys(l3_xenmap) + (50*8)
mov %eax,sym_phys(l3_xenmap) + l3_table_offset(XEN_VIRT_START)*8
/* Hook identity-map and xen-map L3 tables into PML4. */
mov $(sym_phys(l3_identmap)+7),%eax
mov %eax,sym_phys(idle_pg_table) + ( 0*8) /* PML4[ 0]: 1:1 map */
mov %eax,sym_phys(idle_pg_table) + (262*8) /* PML4[262]: 1:1 map */
mov %eax,sym_phys(idle_pg_table) + l4_table_offset(DIRECTMAP_VIRT_START)*8
mov $(sym_phys(l3_xenmap)+7),%eax
mov %eax,sym_phys(idle_pg_table) + (261*8) /* PML4[261]: xen map */
mov %eax,sym_phys(idle_pg_table) + l4_table_offset(XEN_VIRT_START)*8
#else
/* Initialize low and high mappings of memory with 2MB pages */
mov $sym_phys(idle_pg_table_l2),%edi
xen/arch/x86/e820.c
+5 -1
View File
@@ -500,15 +500,19 @@ static void __init machine_specific_memory_setup(
"can be accessed by Xen in 32-bit mode.");
#else
{
unsigned long limit, mpt_limit, pft_limit;
unsigned long limit, mpt_limit, ro_mpt_limit, pft_limit;
limit = DIRECTMAP_VIRT_END - DIRECTMAP_VIRT_START;
mpt_limit = ((RDWR_MPT_VIRT_END - RDWR_MPT_VIRT_START)
/ sizeof(unsigned long)) << PAGE_SHIFT;
ro_mpt_limit = ((RO_MPT_VIRT_END - RO_MPT_VIRT_START)
/ sizeof(unsigned long)) << PAGE_SHIFT;
pft_limit = ((FRAMETABLE_VIRT_END - FRAMETABLE_VIRT_START)
/ sizeof(struct page_info)) << PAGE_SHIFT;
if ( limit > mpt_limit )
limit = mpt_limit;
if ( limit > ro_mpt_limit )
limit = ro_mpt_limit;
if ( limit > pft_limit )
limit = pft_limit;
clip_to_limit(limit,
xen/arch/x86/mm.c
+7
View File
@@ -166,6 +166,13 @@ void __init init_frametable(void)
{
unsigned long nr_pages, page_step, i, mfn;
#ifdef __x86_64__
BUILD_BUG_ON(FRAMETABLE_VIRT_START & ((1UL << L3_PAGETABLE_SHIFT) - 1));
BUILD_BUG_ON(XEN_VIRT_END > FRAMETABLE_VIRT_END);
#else
BUILD_BUG_ON(FRAMETABLE_VIRT_START & ((1UL << L2_PAGETABLE_SHIFT) - 1));
#endif
nr_pages = PFN_UP(max_page * sizeof(*frame_table));
page_step = 1 << (cpu_has_page1gb ? L3_PAGETABLE_SHIFT - PAGE_SHIFT
: L2_PAGETABLE_SHIFT - PAGE_SHIFT);
xen/include/asm-x86/config.h
+16 -15
View File
@@ -148,21 +148,19 @@ extern unsigned int video_mode, video_flags;
* 0xffff828000000000 - 0xffff8283ffffffff [16GB, 2^34 bytes, PML4:261]
* Machine-to-phys translation table.
* 0xffff828400000000 - 0xffff8287ffffffff [16GB, 2^34 bytes, PML4:261]
* Page-frame information array.
* 0xffff828800000000 - 0xffff828bffffffff [16GB, 2^34 bytes, PML4:261]
* ioremap()/fixmap area.
* 0xffff828c00000000 - 0xffff828c3fffffff [1GB, 2^30 bytes, PML4:261]
* 0xffff828800000000 - 0xffff82883fffffff [1GB, 2^30 bytes, PML4:261]
* Compatibility machine-to-phys translation table.
* 0xffff828c40000000 - 0xffff828c7fffffff [1GB, 2^30 bytes, PML4:261]
* 0xffff828840000000 - 0xffff82887fffffff [1GB, 2^30 bytes, PML4:261]
* High read-only compatibility machine-to-phys translation table.
* 0xffff828c80000000 - 0xffff828cbfffffff [1GB, 2^30 bytes, PML4:261]
* 0xffff828880000000 - 0xffff8288bfffffff [1GB, 2^30 bytes, PML4:261]
* Xen text, static data, bss.
* 0xffff828cc0000000 - 0xffff82ffffffffff [461GB, PML4:261]
* 0xffff8288c0000000 - 0xffff82f5ffffffff [437GB, PML4:261]
* Reserved for future use.
* 0xffff830000000000 - 0xffff83ffffffffff [1TB, 2^40 bytes, PML4:262-263]
* 0xffff82f600000000 - 0xffff82ffffffffff [40GB, 2^38 bytes, PML4:261]
* Page-frame information array.
* 0xffff830000000000 - 0xffff87ffffffffff [5TB, 5*2^40 bytes, PML4:262-271]
* 1:1 direct mapping of all physical memory.
* 0xffff840000000000 - 0xffff87ffffffffff [4TB, 2^42 bytes, PML4:264-271]
* Reserved for future use.
* 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511]
* Guest-defined use.
*
@@ -210,11 +208,8 @@ extern unsigned int video_mode, video_flags;
/* Slot 261: machine-to-phys conversion table (16GB). */
#define RDWR_MPT_VIRT_START (PML4_ADDR(261))
#define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + GB(16))
/* Slot 261: page-frame information array (16GB). */
#define FRAMETABLE_VIRT_START (RDWR_MPT_VIRT_END)
#define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + GB(16))
/* Slot 261: ioremap()/fixmap area (16GB). */
#define IOREMAP_VIRT_START (FRAMETABLE_VIRT_END)
#define IOREMAP_VIRT_START RDWR_MPT_VIRT_END
#define IOREMAP_VIRT_END (IOREMAP_VIRT_START + GB(16))
/* Slot 261: compatibility machine-to-phys conversion table (1GB). */
#define RDWR_COMPAT_MPT_VIRT_START IOREMAP_VIRT_END
@@ -225,9 +220,15 @@ extern unsigned int video_mode, video_flags;
/* Slot 261: xen text, static data and bss (1GB). */
#define XEN_VIRT_START (HIRO_COMPAT_MPT_VIRT_END)
#define XEN_VIRT_END (XEN_VIRT_START + GB(1))
/* Slot 262-263: A direct 1:1 mapping of all of physical memory. */
/* Slot 261: page-frame information array (40GB). */
#define FRAMETABLE_VIRT_END DIRECTMAP_VIRT_START
#define FRAMETABLE_SIZE ((DIRECTMAP_SIZE >> PAGE_SHIFT) * \
sizeof(struct page_info))
#define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - FRAMETABLE_SIZE)
/* Slot 262-271: A direct 1:1 mapping of all of physical memory. */
#define DIRECTMAP_VIRT_START (PML4_ADDR(262))
#define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + PML4_ENTRY_BYTES*2)
#define DIRECTMAP_SIZE (PML4_ENTRY_BYTES*10)
#define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + DIRECTMAP_SIZE)
#ifndef __ASSEMBLY__
xen/include/asm-x86/x86_64/page.h
+2 -2
View File
@@ -16,8 +16,8 @@
#define L4_PAGETABLE_ENTRIES (1<<PAGETABLE_ORDER)
#define ROOT_PAGETABLE_ENTRIES L4_PAGETABLE_ENTRIES
#define __PAGE_OFFSET (0xFFFF830000000000)
#define __XEN_VIRT_START (0xFFFF828C80000000)
#define __PAGE_OFFSET DIRECTMAP_VIRT_START
#define __XEN_VIRT_START XEN_VIRT_START
/* These are architectural limits. Current CPUs support only 40-bit phys. */
#define PADDR_BITS 52
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