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x86: Make apicid 32 bits in preparation for x2APIC support.
Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
This commit is contained in:
Keir Fraser committed
1 parent
fe30f626cc
commit
6176d3cd0b
7 files changed
+13
-13
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@@ -73,7 +73,7 @@ static unsigned int __devinitdata num_processors;
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/* Bitmask of physically existing CPUs */
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physid_mask_t phys_cpu_present_map;
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u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
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u32 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
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/*
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* Intel MP BIOS table parsing routines:
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+1
-1
@@ -262,7 +262,7 @@ void __init init_cpu_to_node(void)
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{
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int i;
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for (i = 0; i < NR_CPUS; i++) {
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u8 apicid = x86_cpu_to_apicid[i];
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u32 apicid = x86_cpu_to_apicid[i];
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if (apicid == BAD_APICID)
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continue;
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if (apicid_to_node[apicid] == NUMA_NO_NODE)
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@@ -245,7 +245,7 @@ static void __init init_idle_domain(void)
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static void __init srat_detect_node(int cpu)
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{
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unsigned node;
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u8 apicid = x86_cpu_to_apicid[cpu];
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u32 apicid = x86_cpu_to_apicid[cpu];
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node = apicid_to_node[apicid];
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if ( node == NUMA_NO_NODE )
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@@ -103,8 +103,8 @@ static int __devinitdata tsc_sync_disabled;
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struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
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EXPORT_SYMBOL(cpu_data);
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u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
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{ [0 ... NR_CPUS-1] = 0xff };
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u32 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
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{ [0 ... NR_CPUS-1] = -1U };
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EXPORT_SYMBOL(x86_cpu_to_apicid);
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static void map_cpu_to_logical_apicid(void);
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@@ -543,7 +543,7 @@ extern struct {
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unsigned short ss;
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} stack_start;
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u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
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u32 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
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static void map_cpu_to_logical_apicid(void)
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{
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@@ -21,9 +21,9 @@ static inline void enable_apic_mode(void)
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/*es7000_sw_apic();*/
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}
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#define apicid_to_node(apicid) ((int)apicid_to_node[(u8)apicid])
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#define apicid_to_node(apicid) ((int)apicid_to_node[(u32)apicid])
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extern u8 bios_cpu_apicid[];
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extern u32 bios_cpu_apicid[];
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static inline int cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < NR_CPUS)
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@@ -167,9 +167,9 @@ struct cpuinfo_x86 {
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int x86_cache_size; /* in KB - valid for CPUS which support this call */
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int x86_cache_alignment; /* In bytes */
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int x86_power;
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unsigned char x86_max_cores; /* cpuid returned max cores value */
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unsigned char booted_cores; /* number of cores as seen by OS */
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unsigned char apicid;
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__u32 x86_max_cores; /* cpuid returned max cores value */
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__u32 booted_cores; /* number of cores as seen by OS */
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__u32 apicid;
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unsigned short x86_clflush_size;
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} __cacheline_aligned;
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@@ -22,7 +22,7 @@
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#endif
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#endif
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#define BAD_APICID 0xFFu
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#define BAD_APICID -1U
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#ifdef CONFIG_SMP
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#ifndef __ASSEMBLY__
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@@ -45,7 +45,7 @@ extern void zap_low_mappings(l2_pgentry_t *base);
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#endif
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#define MAX_APICID 256
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extern u8 x86_cpu_to_apicid[];
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extern u32 x86_cpu_to_apicid[];
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#define cpu_physical_id(cpu) x86_cpu_to_apicid[cpu]
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