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Revert "x86/HVM: correct CPUID leaf 80000008 handling"
This reverts commit e7516b4015
(wrongly passing NULLs to hvm_cpuid()).
This commit is contained in:
1 parent
e3f630b73c
commit
651da73a2b
2 files changed
+15
-33
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+3
-20
@@ -2810,8 +2810,6 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx,
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switch ( input )
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{
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unsigned int sub_leaf, _eax, _ebx, _ecx, _edx;
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case 0x1:
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/* Fix up VLAPIC details. */
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*ebx &= 0x00FFFFFFu;
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@@ -2845,6 +2843,8 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx,
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*edx = v->vcpu_id * 2;
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break;
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case 0xd:
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{
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unsigned int sub_leaf, _eax, _ebx, _ecx, _edx;
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/* EBX value of main leaf 0 depends on enabled xsave features */
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if ( count == 0 && v->arch.xcr0 )
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{
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@@ -2861,7 +2861,7 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx,
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}
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}
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break;
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}
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case 0x80000001:
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/* We expose RDTSCP feature to guest only when
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tsc_mode == TSC_MODE_DEFAULT and host_tsc_is_safe() returns 1 */
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@@ -2875,23 +2875,6 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx,
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if ( !(hvm_pae_enabled(v) || hvm_long_mode_enabled(v)) )
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*edx &= ~cpufeat_mask(X86_FEATURE_PSE36);
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break;
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case 0x80000008:
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count = cpuid_eax(0x80000008);
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count = (count >> 16) & 0xff ?: count & 0xff;
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if ( (*eax & 0xff) > count )
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*eax = (*eax & ~0xff) | count;
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hvm_cpuid(1, NULL, NULL, NULL, &_edx);
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count = _edx & (cpufeat_mask(X86_FEATURE_PAE) |
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cpufeat_mask(X86_FEATURE_PSE36)) ? 36 : 32;
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if ( (*eax & 0xff) < count )
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*eax = (*eax & ~0xff) | count;
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hvm_cpuid(0x80000001, NULL, NULL, NULL, &_edx);
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*eax = (*eax & ~0xffff00) | (_edx & cpufeat_mask(X86_FEATURE_LM)
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? 0x3000 : 0x2000);
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break;
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}
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}
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+12
-13
@@ -145,7 +145,7 @@ bool_t is_var_mtrr_overlapped(struct mtrr_state *m)
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static int hvm_mtrr_pat_init(void)
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{
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unsigned int i, j;
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unsigned int i, j, phys_addr;
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memset(&mtrr_epat_tbl, INVALID_MEM_TYPE, sizeof(mtrr_epat_tbl));
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for ( i = 0; i < MTRR_NUM_TYPES; i++ )
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@@ -172,7 +172,11 @@ static int hvm_mtrr_pat_init(void)
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}
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}
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size_or_mask = ~((1 << (paddr_bits - PAGE_SHIFT)) - 1);
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phys_addr = 36;
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if ( cpuid_eax(0x80000000) >= 0x80000008 )
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phys_addr = (uint8_t)cpuid_eax(0x80000008);
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size_or_mask = ~((1 << (phys_addr - PAGE_SHIFT)) - 1);
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return 0;
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}
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@@ -464,21 +468,16 @@ bool_t mtrr_var_range_msr_set(
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type == 4 || type == 5 || type == 6)) )
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return 0;
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if ( d == current->domain )
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phys_addr = 36;
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domain_cpuid(d, 0x80000000, 0, &eax, &ebx, &ecx, &edx);
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if ( eax >= 0x80000008 )
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{
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phys_addr = 36;
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hvm_cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
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if ( eax >= 0x80000008 )
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{
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hvm_cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
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phys_addr = (uint8_t)eax;
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}
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domain_cpuid(d, 0x80000008, 0, &eax, &ebx, &ecx, &edx);
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phys_addr = (uint8_t)eax;
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}
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else
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phys_addr = paddr_bits;
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msr_mask = ~((((uint64_t)1) << phys_addr) - 1);
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msr_mask |= (index & 1) ? 0x7ffUL : 0xf00UL;
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if ( unlikely(msr_content & msr_mask) )
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if ( unlikely(msr_content && (msr_content & msr_mask)) )
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{
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HVM_DBG_LOG(DBG_LEVEL_MSR, "invalid msr content:%"PRIx64"\n",
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msr_content);
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