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No C1-Clock Ramp disabling on AMD processors. The tiny drift
caused by the ramping changes should not cause TSCs to become noticeably out of sync on Xen systems. Signed-off-by: Keir Fraser <keir@xensource.com>
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kaf24@firebug.cl.cam.ac.uk committed
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@@ -3,20 +3,13 @@
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#include <xen/bitops.h>
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#include <xen/mm.h>
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#include <xen/smp.h>
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#include <xen/sched.h>
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#include <asm/io.h>
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#include <asm/msr.h>
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#include <asm/processor.h>
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#include <asm/hvm/vcpu.h>
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#include <asm/hvm/support.h>
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#include "cpu.h"
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#define AMD_C1_CLOCK_RAMP 0x80000084
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#define AMD_ADVPM_TSC_INVARIANT 0x80000007
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/*
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* amd_flush_filter={on,off}. Forcibly Enable or disable the TLB flush
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* filter on AMD 64-bit processors.
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@@ -49,99 +42,6 @@ custom_param("amd_flush_filter", flush_filter);
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extern void vide(void);
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__asm__(".text\n.align 4\nvide: ret");
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/*
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* Check if C1-Clock ramping enabled in PMM7.CpuLowPwrEnh
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* On 8th-Generation cores only. Assume BIOS has setup
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* all Northbridges equivalently.
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*/
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static int c1_ramp_8gen(void)
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{
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u32 l;
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/* Read dev=0x18, function = 3, offset=0x87 */
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l = AMD_C1_CLOCK_RAMP;
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/* fill in dev (18) + function (3) */
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/* direct cfc/cf8 should be safe here */
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l += (((0x18) << 3) + 0x3) << 8;
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outl(l, 0xcf8);
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return (1 & (inl(0xcfc) >> 24));
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}
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/*
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* returns TRUE if ok to use TSC
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*/
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static int use_amd_tsc(struct cpuinfo_x86 *c)
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{
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if (c->x86 < 0xf) {
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/*
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* TSC drift doesn't exist on 7th Gen or less
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* However, OS still needs to consider effects
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* of P-state changes on TSC
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*/
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return 1;
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} else if ( cpuid_edx(AMD_ADVPM_TSC_INVARIANT) & 0x100 ) {
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/*
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* CPUID.AdvPowerMgmtInfo.TscInvariant
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* EDX bit 8, 8000_0007
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* Invariant TSC on 8th Gen or newer, use it
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* (assume all cores have invariant TSC)
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*/
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return 1;
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} else if ((mp_get_num_processors() == 1) && (c->x86_num_cores == 1)) {
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/*
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* OK to use TSC on uni-processor-uni-core
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* However, OS still needs to consider effects
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* of P-state changes on TSC
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*/
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return 1;
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} else if ( (mp_get_num_processors() == 1) && (c->x86 == 0x0f)
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&& !c1_ramp_8gen()) {
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/*
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* Use TSC on 8th Gen uni-proc with C1_ramp off
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* However, OS still needs to consider effects
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* of P-state changes on TSC
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*/
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return 1;
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} else {
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return 0;
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}
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}
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/*
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* Disable C1-Clock ramping if enabled in PMM7.CpuLowPwrEnh
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* On 8th-Generation cores only. Assume BIOS has setup
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* all Northbridges equivalently.
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*/
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static void amd_disable_c1_ramping(void)
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{
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u32 l, h;
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int i;
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for (i=0; i < NR_CPUS;i++) {
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/* Read from the Northbridge for Node x. until we get invalid data */
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/* fill in dev (18 + cpu#) + function (3) */
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l = AMD_C1_CLOCK_RAMP + ((((0x18 + i) << 3) + 0x3) << 8);
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/* direct cfc/cf8 should be safe here */
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outl(l, 0xcf8);
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h = inl(0xcfc);
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if (h != 0xFFFFFFFF) {
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h &= 0xFCFFFFFF; /* clears pmm7[1:0] */
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outl(l, 0xcf8);
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outl(h, 0xcfc);
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printk ("AMD: Disabling C1 Clock Ramping Node #%x\n",i);
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}
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else {
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i = NR_CPUS;
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}
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}
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return;
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}
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static void __init init_amd(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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@@ -347,14 +247,6 @@ static void __init init_amd(struct cpuinfo_x86 *c)
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cpu, c->x86_num_cores, cpu_core_id[cpu]);
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}
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#endif
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/*
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* Prevent TSC drift in non single-processor, single-core platforms
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*/
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if ( !use_amd_tsc(c) && (c->x86 == 0x0f) && c1_ramp_8gen() &&
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(smp_processor_id() == 0)) {
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/* Disable c1 Clock Ramping on all cores */
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amd_disable_c1_ramping();
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}
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#ifdef CONFIG_SVM
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start_svm();
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@@ -730,11 +730,6 @@ void __init get_smp_config (void)
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*/
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}
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int __init mp_get_num_processors(void)
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{
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return num_processors;
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}
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static int __init smp_scan_config (unsigned long base, unsigned long length)
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{
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unsigned int *bp = maddr_to_virt(base);
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@@ -35,7 +35,6 @@ extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base);
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extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 gsi);
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extern void mp_config_acpi_legacy_irqs (void);
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extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low);
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extern int mp_get_num_processors(void);
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#endif /*CONFIG_ACPI_BOOT*/
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#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
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