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X86: expose HLE/RTM features to dom0
Intel recently release 2 new features, HLE and TRM. Refer to http://software.intel.com/file/41417. This patch expose them to dom0. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> Committed-by: Jan Beulich <jbeulich@suse.com>
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Liu, Jinsong committed
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@@ -857,9 +857,11 @@ static void pv_cpuid(struct cpu_user_regs *regs)
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case 0x00000007:
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if ( regs->ecx == 0 )
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b &= (cpufeat_mask(X86_FEATURE_BMI1) |
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cpufeat_mask(X86_FEATURE_HLE) |
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cpufeat_mask(X86_FEATURE_AVX2) |
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cpufeat_mask(X86_FEATURE_BMI2) |
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cpufeat_mask(X86_FEATURE_ERMS) |
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cpufeat_mask(X86_FEATURE_RTM) |
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cpufeat_mask(X86_FEATURE_FSGSBASE));
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else
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b = 0;
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@@ -149,11 +149,13 @@
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */
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#define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
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#define X86_FEATURE_BMI1 (7*32+ 3) /* 1st bit manipulation extensions */
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#define X86_FEATURE_HLE (7*32+ 4) /* Hardware Lock Elision */
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#define X86_FEATURE_AVX2 (7*32+ 5) /* AVX2 instructions */
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#define X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection */
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#define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation extensions */
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#define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
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#define X86_FEATURE_INVPCID (7*32+10) /* Invalidate Process Context ID */
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#define X86_FEATURE_RTM (7*32+11) /* Restricted Transactional Memory */
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#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
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#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
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