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VMX: convert vmx_cpu_based_exec_control
... to a field in the capability/controls struct. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Roger Pau Monné <roger.pau@citrix.com>
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2 files changed
+15
-19
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@@ -164,7 +164,6 @@ static int cf_check parse_ept_param_runtime(const char *s)
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/* Dynamic (run-time adjusted) execution control flags. */
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struct vmx_caps __ro_after_init vmx_caps;
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u32 vmx_cpu_based_exec_control __read_mostly;
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u32 vmx_secondary_exec_control __read_mostly;
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uint64_t vmx_tertiary_exec_control __read_mostly;
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u32 vmx_vmexit_control __read_mostly;
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@@ -265,7 +264,6 @@ static int vmx_init_vmcs_config(bool bsp)
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{
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u32 vmx_basic_msr_low, vmx_basic_msr_high, min, opt;
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struct vmx_caps caps = {};
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u32 _vmx_cpu_based_exec_control;
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u32 _vmx_secondary_exec_control = 0;
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uint64_t _vmx_tertiary_exec_control = 0;
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u64 _vmx_ept_vpid_cap = 0;
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@@ -303,12 +301,12 @@ static int vmx_init_vmcs_config(bool bsp)
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CPU_BASED_MONITOR_TRAP_FLAG |
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CPU_BASED_ACTIVATE_SECONDARY_CONTROLS |
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CPU_BASED_ACTIVATE_TERTIARY_CONTROLS);
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_vmx_cpu_based_exec_control = adjust_vmx_controls(
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caps.cpu_based_exec_control = adjust_vmx_controls(
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"CPU-Based Exec Control", min, opt,
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MSR_IA32_VMX_PROCBASED_CTLS, &mismatch);
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_vmx_cpu_based_exec_control &= ~CPU_BASED_RDTSC_EXITING;
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if ( _vmx_cpu_based_exec_control & CPU_BASED_TPR_SHADOW )
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_vmx_cpu_based_exec_control &=
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caps.cpu_based_exec_control &= ~CPU_BASED_RDTSC_EXITING;
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if ( caps.cpu_based_exec_control & CPU_BASED_TPR_SHADOW )
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caps.cpu_based_exec_control &=
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~(CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING);
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rdmsrl(MSR_IA32_VMX_MISC, _vmx_misc_cap);
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@@ -325,7 +323,7 @@ static int vmx_init_vmcs_config(bool bsp)
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return -EINVAL;
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}
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if ( _vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS )
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if ( caps.cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS )
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{
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min = 0;
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opt = (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
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@@ -355,7 +353,7 @@ static int vmx_init_vmcs_config(bool bsp)
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* "APIC Register Virtualization" and "Virtual Interrupt Delivery"
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* can be set only when "use TPR shadow" is set
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*/
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if ( (_vmx_cpu_based_exec_control & CPU_BASED_TPR_SHADOW) &&
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if ( (caps.cpu_based_exec_control & CPU_BASED_TPR_SHADOW) &&
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opt_apicv_enabled )
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opt |= SECONDARY_EXEC_APIC_REGISTER_VIRT |
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SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
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@@ -366,7 +364,7 @@ static int vmx_init_vmcs_config(bool bsp)
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MSR_IA32_VMX_PROCBASED_CTLS2, &mismatch);
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}
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if ( _vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROLS )
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if ( caps.cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROLS )
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{
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uint64_t opt = (TERTIARY_EXEC_VIRT_SPEC_CTRL |
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TERTIARY_EXEC_EPT_PAGING_WRITE);
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@@ -503,7 +501,6 @@ static int vmx_init_vmcs_config(bool bsp)
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{
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/* First time through. */
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vmx_caps = caps;
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vmx_cpu_based_exec_control = _vmx_cpu_based_exec_control;
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vmx_secondary_exec_control = _vmx_secondary_exec_control;
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vmx_tertiary_exec_control = _vmx_tertiary_exec_control;
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vmx_ept_vpid_cap = _vmx_ept_vpid_cap;
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@@ -536,7 +533,7 @@ static int vmx_init_vmcs_config(bool bsp)
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vmx_caps.pin_based_exec_control, caps.pin_based_exec_control);
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mismatch |= cap_check(
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"CPU-Based Exec Control",
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vmx_cpu_based_exec_control, _vmx_cpu_based_exec_control);
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vmx_caps.cpu_based_exec_control, caps.cpu_based_exec_control);
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mismatch |= cap_check(
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"Secondary Exec Control",
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vmx_secondary_exec_control, _vmx_secondary_exec_control);
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@@ -1116,7 +1113,7 @@ static int construct_vmcs(struct vcpu *v)
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/* VMCS controls. */
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__vmwrite(PIN_BASED_VM_EXEC_CONTROL, vmx_caps.pin_based_exec_control);
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v->arch.hvm.vmx.exec_control = vmx_cpu_based_exec_control;
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v->arch.hvm.vmx.exec_control = vmx_caps.cpu_based_exec_control;
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if ( d->arch.vtsc && !cpu_has_vmx_tsc_scaling )
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v->arch.hvm.vmx.exec_control |= CPU_BASED_RDTSC_EXITING;
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@@ -2230,7 +2227,6 @@ int __init vmx_vmcs_init(void)
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* Make sure all dependent features are off as well.
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*/
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memset(&vmx_caps, 0, sizeof(vmx_caps));
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vmx_cpu_based_exec_control = 0;
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vmx_secondary_exec_control = 0;
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vmx_tertiary_exec_control = 0;
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vmx_vmexit_control = 0;
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@@ -210,7 +210,6 @@ void vmx_vmcs_reload(struct vcpu *v);
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#define CPU_BASED_MONITOR_EXITING 0x20000000U
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#define CPU_BASED_PAUSE_EXITING 0x40000000U
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#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000U
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extern u32 vmx_cpu_based_exec_control;
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#define PIN_BASED_EXT_INTR_MASK 0x00000001
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#define PIN_BASED_NMI_EXITING 0x00000008
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@@ -303,6 +302,7 @@ extern u64 vmx_ept_vpid_cap;
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struct vmx_caps {
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uint64_t basic_msr;
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uint32_t pin_based_exec_control;
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uint32_t cpu_based_exec_control;
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};
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extern struct vmx_caps vmx_caps;
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@@ -314,19 +314,19 @@ extern struct vmx_caps vmx_caps;
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vmx_secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
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#define cpu_has_vmx_tpr_shadow \
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(IS_ENABLED(CONFIG_INTEL_VMX) && \
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vmx_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)
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(vmx_caps.cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
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#define cpu_has_vmx_vnmi \
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(IS_ENABLED(CONFIG_INTEL_VMX) && \
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(vmx_caps.pin_based_exec_control & PIN_BASED_VIRTUAL_NMIS))
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#define cpu_has_vmx_msr_bitmap \
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(IS_ENABLED(CONFIG_INTEL_VMX) && \
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vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_MSR_BITMAP)
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(vmx_caps.cpu_based_exec_control & CPU_BASED_ACTIVATE_MSR_BITMAP))
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#define cpu_has_vmx_secondary_exec_control \
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(IS_ENABLED(CONFIG_INTEL_VMX) && \
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vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
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(vmx_caps.cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
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#define cpu_has_vmx_tertiary_exec_control \
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(IS_ENABLED(CONFIG_INTEL_VMX) && \
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vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROLS)
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(vmx_caps.cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROLS))
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#define cpu_has_vmx_ept \
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(IS_ENABLED(CONFIG_INTEL_VMX) && \
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vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)
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@@ -341,7 +341,7 @@ extern struct vmx_caps vmx_caps;
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vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
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#define cpu_has_monitor_trap_flag \
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(IS_ENABLED(CONFIG_INTEL_VMX) && \
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vmx_cpu_based_exec_control & CPU_BASED_MONITOR_TRAP_FLAG)
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(vmx_caps.cpu_based_exec_control & CPU_BASED_MONITOR_TRAP_FLAG))
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#define cpu_has_vmx_pat \
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(IS_ENABLED(CONFIG_INTEL_VMX) && \
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vmx_vmentry_control & VM_ENTRY_LOAD_GUEST_PAT)
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