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x86/mwait-idle: Add AlderLake-N support
Similar to the other other AlderLake platforms, the C1 and C1E states on
ADL-N are mutually exclusive. Only one of them can be enabled at a time.
C1E is preferred on ADL-N for better energy efficiency.
C6S is also supported on this platform. Its latency is far bigger than
C6, but really close to C8 (PC8), thus it is not exposed as a separate
state.
Suggested-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Suggested-by: Vinay Kumar <vinay.kumar@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
[ rjw: Changelog edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 65c0c2367e9e
x86/cpu: Fix Gracemont uarch
Alderlake N is an E-core only product using Gracemont
micro-architecture. It fits the pre-existing naming scheme perfectly
fine, adhere to it.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20230807150405.686834933@infradead.org
Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 882cdb06b668
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
master commit: 51b956f336
master date: 2025-07-09 11:00:16 +0200
This commit is contained in:
Zhang Rui authored and 
Jan Beulich committed
1 parent
faf408249c
commit
6d0b94a461
1 file changed
+40
@@ -678,6 +678,40 @@ static struct cpuidle_state __read_mostly adl_l_cstates[] = {
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{}
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};
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static const struct cpuidle_state gmt_cstates[] = {
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{
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.name = "C1",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_DISABLED,
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.exit_latency = 1,
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.target_residency = 1,
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},
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{
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.name = "C1E",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 2,
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.target_residency = 4,
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},
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{
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.name = "C6",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 195,
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.target_residency = 585,
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},
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{
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.name = "C8",
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.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 260,
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.target_residency = 1040,
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},
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{
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.name = "C10",
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.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 660,
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.target_residency = 1980,
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},
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{}
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};
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static struct cpuidle_state __read_mostly spr_cstates[] = {
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{
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.name = "C1",
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@@ -1083,6 +1117,10 @@ static struct idle_cpu __read_mostly idle_cpu_adl_l = {
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.state_table = adl_l_cstates,
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};
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static const struct idle_cpu idle_cpu_gmt = {
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.state_table = gmt_cstates,
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};
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static struct idle_cpu __read_mostly idle_cpu_spr = {
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.state_table = spr_cstates,
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.c1e_promotion = C1E_PROMOTION_DISABLE,
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@@ -1148,6 +1186,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconstrel = {
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ICPU(ICELAKE_D, icx),
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ICPU(ALDERLAKE, adl),
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ICPU(ALDERLAKE_L, adl_l),
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ICPU(ATOM_GRACEMONT, gmt),
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ICPU(SAPPHIRERAPIDS_X, spr),
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ICPU(ATOM_GOLDMONT, bxt),
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ICPU(ATOM_GOLDMONT_PLUS, bxt),
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@@ -1386,6 +1425,7 @@ static void __init mwait_idle_state_table_update(void)
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break;
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case INTEL_FAM6_ALDERLAKE:
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case INTEL_FAM6_ALDERLAKE_L:
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case INTEL_FAM6_ATOM_GRACEMONT:
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adl_idle_state_table_update();
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break;
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}
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