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x86: Rename X86_ET_EXT_INTR to X86_ET_INTR and fix function names
The name X86_ET_EXT_INTR came from the VT-x code originally, but it's not
really correct.
The SDM doesn't give a concrete name, and only describes the fields as
"external interrupts". The APM does give a concrete name of INTR, and both
Intel and AMD use the name INTR for related purposes elsewhere; the name
derives originally from #INTR which was a real pin on early processors.
Very importantly, this is distinct from ExtINT which is a type of maskable
interrupt which can be sent in an x86 system.
Therefore rename all {svm,vmx}_*_extint() to {svm,vmx}_*_intr(), as they
pertain to all maskable interrupts, not only to ExtINT interrupts.
No functional change.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
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@@ -230,7 +230,7 @@ int hvm_event_needs_reinjection(uint8_t type, uint8_t vector)
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{
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switch ( type )
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{
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case X86_ET_EXT_INTR:
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case X86_ET_INTR:
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case X86_ET_NMI:
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return 1;
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case X86_ET_HW_EXC:
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@@ -55,14 +55,14 @@ static void svm_inject_nmi(struct vcpu *v)
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vmcb, general1_intercepts | GENERAL1_INTERCEPT_IRET);
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}
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static void svm_inject_extint(struct vcpu *v, int vector)
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static void svm_inject_intr(struct vcpu *v, int vector)
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{
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struct vmcb_struct *vmcb = v->arch.hvm.svm.vmcb;
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intinfo_t event;
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event.raw = 0;
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event.v = true;
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event.type = X86_ET_EXT_INTR;
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event.type = X86_ET_INTR;
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event.vector = vector;
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ASSERT(!vmcb->event_inj.v);
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@@ -225,7 +225,7 @@ void asmlinkage svm_intr_assist(void)
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else
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{
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TRACE(TRC_HVM_INJ_VIRQ, intack.vector, /*fake=*/ 0);
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svm_inject_extint(v, intack.vector);
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svm_inject_intr(v, intack.vector);
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pt_intr_post(v, intack);
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}
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@@ -2808,7 +2808,7 @@ void asmlinkage svm_vmexit_handler(void)
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vmcb->exit_int_info.vector == X86_EXC_OF )
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break;
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/* Fallthrough */
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case X86_ET_EXT_INTR:
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case X86_ET_INTR:
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case X86_ET_NMI:
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insn_len = 0;
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break;
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@@ -182,7 +182,7 @@ static int nvmx_intr_intercept(struct vcpu *v, struct hvm_intack intack)
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if ( intack.source == hvm_intsrc_pic ||
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intack.source == hvm_intsrc_lapic )
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{
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vmx_inject_extint(intack.vector, intack.source);
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vmx_inject_intr(intack.vector, intack.source);
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ctrl = get_vvmcs(v, VM_EXIT_CONTROLS);
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if ( ctrl & VM_EXIT_ACK_INTR_ON_EXIT )
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@@ -202,7 +202,7 @@ static int nvmx_intr_intercept(struct vcpu *v, struct hvm_intack intack)
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}
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else if ( intack.source == hvm_intsrc_vector )
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{
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vmx_inject_extint(intack.vector, intack.source);
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vmx_inject_intr(intack.vector, intack.source);
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return 1;
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}
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}
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@@ -389,7 +389,7 @@ void asmlinkage vmx_intr_assist(void)
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else
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{
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TRACE(TRC_HVM_INJ_VIRQ, intack.vector, /*fake=*/ 0);
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vmx_inject_extint(intack.vector, intack.source);
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vmx_inject_intr(intack.vector, intack.source);
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pt_intr_post(v, intack);
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}
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@@ -2022,7 +2022,7 @@ static void __vmx_inject_exception(int trap, int type, int error_code)
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curr->arch.hvm.vmx.vmx_emulate = 1;
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}
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void vmx_inject_extint(int trap, uint8_t source)
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void vmx_inject_intr(int trap, uint8_t source)
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{
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struct vcpu *v = current;
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u32 pin_based_cntrl;
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@@ -2032,13 +2032,13 @@ void vmx_inject_extint(int trap, uint8_t source)
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if ( pin_based_cntrl & PIN_BASED_EXT_INTR_MASK ) {
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nvmx_enqueue_n2_exceptions (v,
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INTR_INFO_VALID_MASK |
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MASK_INSR(X86_ET_EXT_INTR, INTR_INFO_INTR_TYPE_MASK) |
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MASK_INSR(X86_ET_INTR, INTR_INFO_INTR_TYPE_MASK) |
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MASK_INSR(trap, INTR_INFO_VECTOR_MASK),
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X86_EVENT_NO_EC, source);
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return;
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}
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}
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__vmx_inject_exception(trap, X86_ET_EXT_INTR, X86_EVENT_NO_EC);
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__vmx_inject_exception(trap, X86_ET_INTR, X86_EVENT_NO_EC);
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}
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void vmx_inject_nmi(void)
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@@ -3846,7 +3846,7 @@ gp_fault:
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return X86EMUL_EXCEPTION;
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}
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static void vmx_do_extint(struct cpu_user_regs *regs)
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static void vmx_do_intr(struct cpu_user_regs *regs)
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{
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unsigned long vector;
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@@ -4219,7 +4219,7 @@ void asmlinkage vmx_vmexit_handler(struct cpu_user_regs *regs)
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switch ( (uint16_t)exit_reason )
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{
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case EXIT_REASON_EXTERNAL_INTERRUPT:
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vmx_do_extint(regs);
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vmx_do_intr(regs);
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break;
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case EXIT_REASON_EXCEPTION_NMI:
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__vmread(VM_EXIT_INTR_INFO, &intr_info);
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@@ -1346,7 +1346,7 @@ static void sync_exception_state(struct vcpu *v)
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switch ( MASK_EXTR(nvmx->intr.intr_info, INTR_INFO_INTR_TYPE_MASK) )
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{
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case X86_ET_EXT_INTR:
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case X86_ET_INTR:
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/* rename exit_reason to EXTERNAL_INTERRUPT */
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set_vvmcs(v, VM_EXIT_REASON, EXIT_REASON_EXTERNAL_INTERRUPT);
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set_vvmcs(v, EXIT_QUALIFICATION, 0);
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@@ -484,7 +484,7 @@ static inline void vpid_sync_all(void)
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int cf_check vmx_guest_x86_mode(struct vcpu *v);
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unsigned int vmx_get_cpl(void);
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void vmx_inject_extint(int trap, uint8_t source);
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void vmx_inject_intr(int trap, uint8_t source);
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void vmx_inject_nmi(void);
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void ept_walk_table(struct domain *d, unsigned long gfn);
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@@ -221,7 +221,7 @@
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* These encodings were first used in VMCB/VMCS fields, but have become
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* architectural in the FRED spec.
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*/
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#define X86_ET_EXT_INTR 0 /* External Interrupt */
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#define X86_ET_INTR 0 /* External Interrupt */
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#define X86_ET_NMI 2 /* NMI */
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#define X86_ET_HW_EXC 3 /* Hardware Exception (#PF/#GP/etc) */
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#define X86_ET_SW_INT 4 /* Software Interrupt (INT $n) */
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@@ -1041,7 +1041,7 @@ void show_execution_state_nmi(const cpumask_t *mask, bool show_all)
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static const char *x86_et_name(unsigned int type)
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{
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static const char *const names[] = {
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[X86_ET_EXT_INTR] = "EXT_INTR",
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[X86_ET_INTR] = "INTR",
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[X86_ET_NMI] = "NMI",
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[X86_ET_HW_EXC] = "HW_EXC",
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[X86_ET_SW_INT] = "SW_INT",
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@@ -2295,7 +2295,7 @@ void asmlinkage entry_from_pv(struct cpu_user_regs *regs)
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switch ( type )
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{
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case X86_ET_EXT_INTR:
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case X86_ET_INTR:
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return do_IRQ(regs);
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case X86_ET_NMI:
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@@ -2606,7 +2606,7 @@ void asmlinkage entry_from_xen(struct cpu_user_regs *regs)
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switch ( type )
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{
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case X86_ET_EXT_INTR:
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case X86_ET_INTR:
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return do_IRQ(regs);
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case X86_ET_NMI:
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@@ -8691,7 +8691,7 @@ static void __init __maybe_unused build_assertions(void)
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BUILD_BUG_ON(x86_seg_gs != 5);
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/* Check X86_ET_* against VMCB EVENTINJ and VMCS INTR_INFO type fields. */
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BUILD_BUG_ON(X86_ET_EXT_INTR != 0);
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BUILD_BUG_ON(X86_ET_INTR != 0);
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BUILD_BUG_ON(X86_ET_NMI != 2);
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BUILD_BUG_ON(X86_ET_HW_EXC != 3);
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BUILD_BUG_ON(X86_ET_SW_INT != 4);
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