x86: Rename X86_ET_EXT_INTR to X86_ET_INTR and fix function names

The name X86_ET_EXT_INTR came from the VT-x code originally, but it's not
really correct.

The SDM doesn't give a concrete name, and only describes the fields as
"external interrupts".  The APM does give a concrete name of INTR, and both
Intel and AMD use the name INTR for related purposes elsewhere; the name
derives originally from #INTR which was a real pin on early processors.

Very importantly, this is distinct from ExtINT which is a type of maskable
interrupt which can be sent in an x86 system.

Therefore rename all {svm,vmx}_*_extint() to {svm,vmx}_*_intr(), as they
pertain to all maskable interrupts, not only to ExtINT interrupts.

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
This commit is contained in:
Andrew Cooper committed 2026-09-11 18:24:25 +01:00
1 parent acd87f99ac
commit 73df85da4f
10 files changed
+20 -20

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+1 -1
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@@ -230,7 +230,7 @@ int hvm_event_needs_reinjection(uint8_t type, uint8_t vector)
{
switch ( type )
{
case X86_ET_EXT_INTR:
case X86_ET_INTR:
case X86_ET_NMI:
return 1;
case X86_ET_HW_EXC:
+3 -3
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@@ -55,14 +55,14 @@ static void svm_inject_nmi(struct vcpu *v)
vmcb, general1_intercepts | GENERAL1_INTERCEPT_IRET);
}
static void svm_inject_extint(struct vcpu *v, int vector)
static void svm_inject_intr(struct vcpu *v, int vector)
{
struct vmcb_struct *vmcb = v->arch.hvm.svm.vmcb;
intinfo_t event;
event.raw = 0;
event.v = true;
event.type = X86_ET_EXT_INTR;
event.type = X86_ET_INTR;
event.vector = vector;
ASSERT(!vmcb->event_inj.v);
@@ -225,7 +225,7 @@ void asmlinkage svm_intr_assist(void)
else
{
TRACE(TRC_HVM_INJ_VIRQ, intack.vector, /*fake=*/ 0);
svm_inject_extint(v, intack.vector);
svm_inject_intr(v, intack.vector);
pt_intr_post(v, intack);
}
+1 -1
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@@ -2808,7 +2808,7 @@ void asmlinkage svm_vmexit_handler(void)
vmcb->exit_int_info.vector == X86_EXC_OF )
break;
/* Fallthrough */
case X86_ET_EXT_INTR:
case X86_ET_INTR:
case X86_ET_NMI:
insn_len = 0;
break;
+3 -3
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@@ -182,7 +182,7 @@ static int nvmx_intr_intercept(struct vcpu *v, struct hvm_intack intack)
if ( intack.source == hvm_intsrc_pic ||
intack.source == hvm_intsrc_lapic )
{
vmx_inject_extint(intack.vector, intack.source);
vmx_inject_intr(intack.vector, intack.source);
ctrl = get_vvmcs(v, VM_EXIT_CONTROLS);
if ( ctrl & VM_EXIT_ACK_INTR_ON_EXIT )
@@ -202,7 +202,7 @@ static int nvmx_intr_intercept(struct vcpu *v, struct hvm_intack intack)
}
else if ( intack.source == hvm_intsrc_vector )
{
vmx_inject_extint(intack.vector, intack.source);
vmx_inject_intr(intack.vector, intack.source);
return 1;
}
}
@@ -389,7 +389,7 @@ void asmlinkage vmx_intr_assist(void)
else
{
TRACE(TRC_HVM_INJ_VIRQ, intack.vector, /*fake=*/ 0);
vmx_inject_extint(intack.vector, intack.source);
vmx_inject_intr(intack.vector, intack.source);
pt_intr_post(v, intack);
}
+5 -5
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@@ -2022,7 +2022,7 @@ static void __vmx_inject_exception(int trap, int type, int error_code)
curr->arch.hvm.vmx.vmx_emulate = 1;
}
void vmx_inject_extint(int trap, uint8_t source)
void vmx_inject_intr(int trap, uint8_t source)
{
struct vcpu *v = current;
u32 pin_based_cntrl;
@@ -2032,13 +2032,13 @@ void vmx_inject_extint(int trap, uint8_t source)
if ( pin_based_cntrl & PIN_BASED_EXT_INTR_MASK ) {
nvmx_enqueue_n2_exceptions (v,
INTR_INFO_VALID_MASK |
MASK_INSR(X86_ET_EXT_INTR, INTR_INFO_INTR_TYPE_MASK) |
MASK_INSR(X86_ET_INTR, INTR_INFO_INTR_TYPE_MASK) |
MASK_INSR(trap, INTR_INFO_VECTOR_MASK),
X86_EVENT_NO_EC, source);
return;
}
}
__vmx_inject_exception(trap, X86_ET_EXT_INTR, X86_EVENT_NO_EC);
__vmx_inject_exception(trap, X86_ET_INTR, X86_EVENT_NO_EC);
}
void vmx_inject_nmi(void)
@@ -3846,7 +3846,7 @@ gp_fault:
return X86EMUL_EXCEPTION;
}
static void vmx_do_extint(struct cpu_user_regs *regs)
static void vmx_do_intr(struct cpu_user_regs *regs)
{
unsigned long vector;
@@ -4219,7 +4219,7 @@ void asmlinkage vmx_vmexit_handler(struct cpu_user_regs *regs)
switch ( (uint16_t)exit_reason )
{
case EXIT_REASON_EXTERNAL_INTERRUPT:
vmx_do_extint(regs);
vmx_do_intr(regs);
break;
case EXIT_REASON_EXCEPTION_NMI:
__vmread(VM_EXIT_INTR_INFO, &intr_info);
+1 -1
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@@ -1346,7 +1346,7 @@ static void sync_exception_state(struct vcpu *v)
switch ( MASK_EXTR(nvmx->intr.intr_info, INTR_INFO_INTR_TYPE_MASK) )
{
case X86_ET_EXT_INTR:
case X86_ET_INTR:
/* rename exit_reason to EXTERNAL_INTERRUPT */
set_vvmcs(v, VM_EXIT_REASON, EXIT_REASON_EXTERNAL_INTERRUPT);
set_vvmcs(v, EXIT_QUALIFICATION, 0);
+1 -1
View File
@@ -484,7 +484,7 @@ static inline void vpid_sync_all(void)
int cf_check vmx_guest_x86_mode(struct vcpu *v);
unsigned int vmx_get_cpl(void);
void vmx_inject_extint(int trap, uint8_t source);
void vmx_inject_intr(int trap, uint8_t source);
void vmx_inject_nmi(void);
void ept_walk_table(struct domain *d, unsigned long gfn);
+1 -1
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@@ -221,7 +221,7 @@
* These encodings were first used in VMCB/VMCS fields, but have become
* architectural in the FRED spec.
*/
#define X86_ET_EXT_INTR 0 /* External Interrupt */
#define X86_ET_INTR 0 /* External Interrupt */
#define X86_ET_NMI 2 /* NMI */
#define X86_ET_HW_EXC 3 /* Hardware Exception (#PF/#GP/etc) */
#define X86_ET_SW_INT 4 /* Software Interrupt (INT $n) */
+3 -3
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@@ -1041,7 +1041,7 @@ void show_execution_state_nmi(const cpumask_t *mask, bool show_all)
static const char *x86_et_name(unsigned int type)
{
static const char *const names[] = {
[X86_ET_EXT_INTR] = "EXT_INTR",
[X86_ET_INTR] = "INTR",
[X86_ET_NMI] = "NMI",
[X86_ET_HW_EXC] = "HW_EXC",
[X86_ET_SW_INT] = "SW_INT",
@@ -2295,7 +2295,7 @@ void asmlinkage entry_from_pv(struct cpu_user_regs *regs)
switch ( type )
{
case X86_ET_EXT_INTR:
case X86_ET_INTR:
return do_IRQ(regs);
case X86_ET_NMI:
@@ -2606,7 +2606,7 @@ void asmlinkage entry_from_xen(struct cpu_user_regs *regs)
switch ( type )
{
case X86_ET_EXT_INTR:
case X86_ET_INTR:
return do_IRQ(regs);
case X86_ET_NMI:
+1 -1
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@@ -8691,7 +8691,7 @@ static void __init __maybe_unused build_assertions(void)
BUILD_BUG_ON(x86_seg_gs != 5);
/* Check X86_ET_* against VMCB EVENTINJ and VMCS INTR_INFO type fields. */
BUILD_BUG_ON(X86_ET_EXT_INTR != 0);
BUILD_BUG_ON(X86_ET_INTR != 0);
BUILD_BUG_ON(X86_ET_NMI != 2);
BUILD_BUG_ON(X86_ET_HW_EXC != 3);
BUILD_BUG_ON(X86_ET_SW_INT != 4);
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