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x86/spec-ctrl: Rename retpoline_safe() to retpoline_calculations()
This is prep work, split out to simply the diff on the following change.
* Rename to retpoline_calculations(), and call unconditionally. It is
shortly going to synthesise missing enumerations required for guest safety.
* For the model check switch statement, store the result in a variable and
break rather than returning directly.
No functional change.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
(cherry picked from commit 724c0d94ff)
This commit is contained in:
1 parent
3ac6887c3e
commit
78a4031ed9
1 file changed
+26
-15
+26
-15
@@ -587,9 +587,10 @@ static bool __init check_smt_enabled(void)
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}
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/* Calculate whether Retpoline is known-safe on this CPU. */
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static bool __init retpoline_safe(void)
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static bool __init retpoline_calculations(void)
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{
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unsigned int ucode_rev = this_cpu(cpu_sig).rev;
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bool safe = false;
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if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
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return true;
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@@ -627,29 +628,31 @@ static bool __init retpoline_safe(void)
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case 0x3f: /* Haswell EX/EP */
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case 0x45: /* Haswell D */
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case 0x46: /* Haswell H */
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return true;
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safe = true;
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break;
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/*
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* Broadwell processors are retpoline-safe after specific microcode
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* versions.
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*/
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case 0x3d: /* Broadwell */
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return ucode_rev >= 0x2a;
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safe = ucode_rev >= 0x2a; break;
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case 0x47: /* Broadwell H */
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return ucode_rev >= 0x1d;
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safe = ucode_rev >= 0x1d; break;
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case 0x4f: /* Broadwell EP/EX */
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return ucode_rev >= 0xb000021;
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safe = ucode_rev >= 0xb000021; break;
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case 0x56: /* Broadwell D */
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switch ( boot_cpu_data.x86_mask )
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{
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case 2: return ucode_rev >= 0x15;
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case 3: return ucode_rev >= 0x7000012;
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case 4: return ucode_rev >= 0xf000011;
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case 5: return ucode_rev >= 0xe000009;
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case 2: safe = ucode_rev >= 0x15; break;
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case 3: safe = ucode_rev >= 0x7000012; break;
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case 4: safe = ucode_rev >= 0xf000011; break;
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case 5: safe = ucode_rev >= 0xe000009; break;
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default:
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printk("Unrecognised CPU stepping %#x - assuming not reptpoline safe\n",
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boot_cpu_data.x86_mask);
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return false;
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safe = false;
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break;
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}
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break;
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@@ -663,7 +666,8 @@ static bool __init retpoline_safe(void)
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case 0x67: /* Cannonlake? */
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case 0x8e: /* Kabylake M */
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case 0x9e: /* Kabylake D */
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return false;
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safe = false;
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break;
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/*
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* Atom processors before Goldmont Plus/Gemini Lake are retpoline-safe.
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@@ -682,13 +686,17 @@ static bool __init retpoline_safe(void)
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case 0x5c: /* Goldmont */
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case 0x5f: /* Denverton */
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case 0x85: /* Knights Mill */
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return true;
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safe = true;
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break;
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default:
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printk("Unrecognised CPU model %#x - assuming not reptpoline safe\n",
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boot_cpu_data.x86_model);
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return false;
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safe = false;
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break;
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}
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return safe;
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}
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/* Calculate whether this CPU speculates past #NM */
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@@ -1092,7 +1100,7 @@ void __init init_speculation_mitigations(void)
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{
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enum ind_thunk thunk = THUNK_DEFAULT;
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bool has_spec_ctrl, ibrs = false, hw_smt_enabled;
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bool cpu_has_bug_taa;
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bool cpu_has_bug_taa, retpoline_safe;
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hw_smt_enabled = check_smt_enabled();
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@@ -1121,6 +1129,9 @@ void __init init_speculation_mitigations(void)
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thunk = THUNK_JMP;
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}
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/* Determine if retpoline is safe on this CPU. */
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retpoline_safe = retpoline_calculations();
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/*
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* Has the user specified any custom BTI mitigations? If so, follow their
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* instructions exactly and disable all heuristics.
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@@ -1142,7 +1153,7 @@ void __init init_speculation_mitigations(void)
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* On all hardware, we'd like to use retpoline in preference to
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* IBRS, but only if it is safe on this hardware.
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*/
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if ( retpoline_safe() )
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if ( retpoline_safe )
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thunk = THUNK_RETPOLINE;
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else if ( has_spec_ctrl )
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ibrs = true;
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