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xen/arm: traps: drop unreachable stage 2 decoding from panic_PAR()
panic_PAR() is only called from va_to_par(), which translates using
__va_to_par(), i.e. "at s1e2r" on arm64 and ATS1HR on arm32. Both
perform an EL2 stage 1 only translation, so PAR.S (PAR_STAGE2) and
PAR.PTW (PAR_STAGE21) can never be set.
This has been the case since commit a14447dbcf ("xen: arm: do not
panic when failing to translate a guest address"), which made
gva_to_par() and gva_to_ipa() return -EFAULT instead of calling
panic_PAR() for guest translations.
Print stage 1 unconditionally and keep an ASSERT() to document the
invariant. PAR_STAGE21 has no user left, so drop it. While at it, fix
the spacing in the decode_fsc() call.
No functional change intended.
Signed-off-by: Michal Orzel <michal.orzel@amd.com>
Reviewed-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
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@@ -507,7 +507,6 @@ extern register_t __cpu_logical_map[];
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/* .... If F == 1 */
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#define PAR_FSC_SHIFT (1)
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#define PAR_FSC_MASK (_AC(0x3f,U)<<PAR_FSC_SHIFT)
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#define PAR_STAGE21 (_AC(1,U)<<8) /* Stage 2 Fault During Stage 1 Walk */
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#define PAR_STAGE2 (_AC(1,U)<<9) /* Stage 2 Fault */
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/* If F == 0 */
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@@ -379,16 +379,17 @@ void panic_PAR(uint64_t par)
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{
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const char *msg;
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int level = -1;
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int stage = par & PAR_STAGE2 ? 2 : 1;
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int second_in_first = !!(par & PAR_STAGE21);
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msg = decode_fsc( (par&PAR_FSC_MASK) >> PAR_FSC_SHIFT, &level);
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/*
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* The only caller translates using "at s1e2r" (arm64) or ATS1HR
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* (arm32), i.e. an EL2 stage 1 only translation.
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*/
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ASSERT(!(par & PAR_STAGE2));
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printk("PAR: %016"PRIx64": %s stage %d%s%s\n",
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par, msg,
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stage,
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second_in_first ? " during second stage lookup" : "",
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fsc_level_str(level));
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msg = decode_fsc((par & PAR_FSC_MASK) >> PAR_FSC_SHIFT, &level);
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printk("PAR: %016"PRIx64": %s stage 1%s\n",
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par, msg, fsc_level_str(level));
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panic("Error during Hypervisor-to-physical address translation\n");
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}
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