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x86: Add bit definitions for Automatic IBRS
This is an AMD feature to reduce the IBRS handling overhead. Once enabled, processes running at CPL=0 are automatically IBRS-protected even if SPEC_CTRL.IBRS is not set. Furthermore, the RAS/RSB is cleared on VMEXIT. The feature is exposed in CPUID and toggled in EFER. Signed-off-by: Alejandro Vallejo <alejandro.vallejo@cloud.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Alejandro Vallejo authored and Andrew Cooper committed
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@@ -317,6 +317,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
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{"lfence+", 0x80000021, NA, CPUID_REG_EAX, 2, 1},
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{"nscb", 0x80000021, NA, CPUID_REG_EAX, 6, 1},
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{"auto-ibrs", 0x80000021, NA, CPUID_REG_EAX, 8, 1},
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{"cpuid-user-dis", 0x80000021, NA, CPUID_REG_EAX, 17, 1},
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{"maxhvleaf", 0x40000000, NA, CPUID_REG_EAX, 0, 8},
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@@ -199,6 +199,7 @@ static const char *const str_e21a[32] =
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{
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[ 2] = "lfence+",
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[ 6] = "nscb",
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[ 8] = "auto-ibrs",
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/* 16 */ [17] = "cpuid-user-dis",
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};
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@@ -161,6 +161,7 @@ static inline bool boot_cpu_has(unsigned int feat)
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#define cpu_has_amd_ssbd boot_cpu_has(X86_FEATURE_AMD_SSBD)
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#define cpu_has_virt_ssbd boot_cpu_has(X86_FEATURE_VIRT_SSBD)
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#define cpu_has_ssb_no boot_cpu_has(X86_FEATURE_SSB_NO)
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#define cpu_has_auto_ibrs boot_cpu_has(X86_FEATURE_AUTO_IBRS)
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/* CPUID level 0x00000007:0.edx */
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#define cpu_has_avx512_4vnniw boot_cpu_has(X86_FEATURE_AVX512_4VNNIW)
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@@ -175,6 +175,7 @@
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#define EFER_NXE (_AC(1, ULL) << 11) /* No Execute Enable */
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#define EFER_SVME (_AC(1, ULL) << 12) /* Secure Virtual Machine Enable */
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#define EFER_FFXSE (_AC(1, ULL) << 14) /* Fast FXSAVE/FXRSTOR */
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#define EFER_AIBRSE (_AC(1, ULL) << 21) /* Automatic IBRS Enable */
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#define EFER_KNOWN_MASK \
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(EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE)
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@@ -287,6 +287,7 @@ XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA Instructions */
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/* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */
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XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */
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XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base (and limit too) */
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XEN_CPUFEATURE(AUTO_IBRS, 11*32+ 8) /* Automatic IBRS */
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XEN_CPUFEATURE(CPUID_USER_DIS, 11*32+17) /* CPUID disable for CPL > 0 software */
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/* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
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