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x86/platform: Adjust temperature sensors MSRs
Temperature sensors MSR were previously assumed to be available when "DTS"
CPUID bit is set. This is not really the case :
* MSR_IA32_THERM_STATUS is gated behind ACPI CPUID bit, only DTS-related bits
of this MSR are gated behind the DTS CPUID
* MSR_PACKAGE_THERM_STATUS is gated behind "PTM" CPUID
Also adjust the MSR_TEMPERATURE_TARGET which is not architectural, but stable
in practice, and required to be exposed for reliably querying CPU temperature.
Fixes: 615c9f3f82 ("x86/platform: Expose DTS sensors MSR")
Reported-by: Tu Dinh <ngoc-tu.dinh@vates.tech>
Signed-off-by: Teddy Astie <teddy.astie@vates.tech>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
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@@ -89,9 +89,26 @@ static bool msr_read_allowed(unsigned int msr)
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return cpu_has_srbds_ctrl;
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case MSR_IA32_THERM_STATUS:
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return host_cpu_policy.basic.acpi;
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/*
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* This MSR is present on most Intel Core-family CPUs since Nehalem but is not an
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* architectural MSR. No CPUID bit enumerates this MSR.
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*
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* This MSR exposes "temperature target" that is needed to compute the CPU
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* temperature. The "temperature target" is a model specific value, and this MSR is
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* the only known method of getting the one used for the CPU. On some CPU models with
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* Intel SST-PP, the "temperature target" can vary over time.
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*
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* We assume all Intel CPUs with DTS may support this MSR; but reads can fail in case
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* the platform doesn't actually support this MSR.
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*/
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case MSR_TEMPERATURE_TARGET:
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return boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
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host_cpu_policy.basic.digital_temp_sensor;
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case MSR_PACKAGE_THERM_STATUS:
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return host_cpu_policy.basic.digital_temp_sensor;
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return host_cpu_policy.basic.pkg_therm_mgmt;
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}
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if ( ppin_msr && msr == ppin_msr )
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@@ -132,7 +132,7 @@ struct cpu_policy
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:1,
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:1,
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:1,
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:1,
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pkg_therm_mgmt:1,
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hwp:1,
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hwp_interrupt:1,
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hwp_activity_window:1,
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