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bitkeeper revision 1.15.1.8 (3e2d5b75k3SSnLdVzMd7kREO_EvMLw)
Added macros and counters to page table flushes. macros and the counter are in a new header file -- flushtlb.h
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akw27@labyrinth.cl.cam.ac.uk committed
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5 files changed
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@@ -134,6 +134,7 @@
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3e20b82fl1jmQiKdLy7fxMcutfpjWA xen-2.4.16/include/asm-i386/domain_page.h
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3ddb79c2O729EttZTYu1c8LcsUO_GQ xen-2.4.16/include/asm-i386/elf.h
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3ddb79c3NU8Zy40OTrq3D-i30Y3t4A xen-2.4.16/include/asm-i386/fixmap.h
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3e2d29944GI24gf7vOP_7x8EyuqxeA xen-2.4.16/include/asm-i386/flushtlb.h
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3ddb79c39o75zPP0T1aQQ4mNrCAN2w xen-2.4.16/include/asm-i386/hardirq.h
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3ddb79c3BFEIwXR4IsWbwp4BoL4DkA xen-2.4.16/include/asm-i386/hdreg.h
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3ddb79c3TMDjkxVndKFKnGiwY0HzDg xen-2.4.16/include/asm-i386/i387.h
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@@ -11,6 +11,7 @@
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#include <xeno/dom0_ops.h>
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#include <asm/io.h>
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#include <asm/domain_page.h>
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#include <asm/flushtlb.h>
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rwlock_t tasklist_lock __cacheline_aligned = RW_LOCK_UNLOCKED;
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@@ -581,8 +582,7 @@ int setup_guestos(struct task_struct *p, dom0_newdomain_t *params)
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/* Install the new page tables. */
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__cli();
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__asm__ __volatile__ (
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"mov %%eax,%%cr3" : : "a" (pagetable_val(p->mm.pagetable)));
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__write_cr3_counted(pagetable_val(p->mm.pagetable));
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/* Copy the guest OS image. */
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src = (char *)__va(mod[0].mod_start + 12);
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@@ -657,8 +657,7 @@ int setup_guestos(struct task_struct *p, dom0_newdomain_t *params)
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}
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/* Reinstate the caller's page tables. */
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__asm__ __volatile__ (
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"mov %%eax,%%cr3" : : "a" (pagetable_val(current->mm.pagetable)));
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__write_cr3_counted(pagetable_val(current->mm.pagetable));
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__sti();
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new_thread(p,
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@@ -171,6 +171,7 @@
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#include <xeno/sched.h>
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#include <xeno/errno.h>
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#include <asm/page.h>
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#include <asm/flushtlb.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/domain_page.h>
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@@ -766,9 +767,7 @@ int do_process_page_updates(page_update_request_t *updates, int count)
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if ( tlb_flush[smp_processor_id()] )
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{
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tlb_flush[smp_processor_id()] = 0;
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__asm__ __volatile__ (
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"movl %%eax,%%cr3" : :
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"a" (pagetable_val(current->mm.pagetable)));
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__write_cr3_counted(pagetable_val(current->mm.pagetable));
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}
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return(0);
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@@ -0,0 +1,48 @@
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/******************************************************************************
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* flushtlb.h
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*
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* TLB flush macros that count flushes. Counting is used to enforce
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* zero-copy safety, particularily for the network code.
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*
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* akw - Jan 21, 2003
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*/
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#ifndef __FLUSHTLB_H
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#define __FLUSHTLB_H
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#include <xeno/smp.h>
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unsigned long tlb_flush_count[NR_CPUS];
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//#if 0
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#define __read_cr3(__var) \
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do { \
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__asm__ __volatile ( \
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"movl %%cr3, %0;" \
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: "=r" (__var)); \
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} while (0)
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//#endif
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#define __write_cr3_counted(__pa) \
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do { \
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__asm__ __volatile__ ( \
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"movl %0, %%cr3;" \
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:: "r" (__pa) \
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: "memory"); \
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tlb_flush_count[smp_processor_id()]++; \
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} while (0)
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//#endif
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#define __flush_tlb_counted() \
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do { \
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unsigned int tmpreg; \
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\
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__asm__ __volatile__( \
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"movl %%cr3, %0; # flush TLB \n" \
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"movl %0, %%cr3; " \
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: "=r" (tmpreg) \
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:: "memory"); \
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tlb_flush_count[smp_processor_id()]++; \
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} while (0)
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#endif
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@@ -91,36 +91,36 @@ typedef struct { unsigned long pt_lo; } pagetable_t;
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#include <asm/processor.h>
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#include <asm/fixmap.h>
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#include <asm/bitops.h>
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#include <asm/flushtlb.h>
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extern l2_pgentry_t idle0_pg_table[ENTRIES_PER_L2_PAGETABLE];
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extern l2_pgentry_t *idle_pg_table[NR_CPUS];
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extern void paging_init(void);
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#define __flush_tlb() \
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do { \
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unsigned int tmpreg; \
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\
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__asm__ __volatile__( \
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"movl %%cr3, %0; # flush TLB \n" \
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"movl %0, %%cr3; \n" \
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: "=r" (tmpreg) \
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:: "memory"); \
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} while (0)
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#define __flush_tlb() __flush_tlb_counted()
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/* Flush global pages as well. */
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#define __pge_off() \
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do { \
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__asm__ __volatile__( \
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"movl %0, %%cr4; # turn off PGE " \
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:: "r" (mmu_cr4_features & ~X86_CR4_PGE)); \
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} while (0)
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#define __pge_on() \
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do { \
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__asm__ __volatile__( \
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"movl %0, %%cr4; # turn off PGE " \
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:: "r" (mmu_cr4_features)); \
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} while (0)
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#define __flush_tlb_all() \
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do { \
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unsigned int tmpreg; \
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\
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__asm__ __volatile__( \
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"movl %1, %%cr4; # turn off PGE \n" \
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"movl %%cr3, %0; # flush TLB \n" \
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"movl %0, %%cr3; \n" \
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"movl %2, %%cr4; # turn PGE back on \n" \
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: "=&r" (tmpreg) \
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: "r" (mmu_cr4_features & ~X86_CR4_PGE), \
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"r" (mmu_cr4_features) \
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: "memory"); \
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__pge_off(); \
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__flush_tlb_counted(); \
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__pge_on(); \
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} while (0)
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#define __flush_tlb_one(__addr) \
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