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Code Issues Activity

printk: prefer %#x et at over 0x%x

Browse Source 
Performance is not an issue with printk(), so let the function do
minimally more work and instead save a byte per affected format
specifier.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
This commit is contained in:
Jan Beulich committed 2012-09-21 14:25:12 +02:00
1 parent 724b55f48a
commit 8a858447e9
51 files changed
+201 -205
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xen/arch/x86/acpi/boot.c
+2 -2
View File
@@ -341,14 +341,14 @@ acpi_fadt_parse_sleep_info(struct acpi_table_fadt *fadt)
}
if (facs->length < 24) {
printk(KERN_ERR PREFIX "Invalid FACS table length: 0x%x",
printk(KERN_ERR PREFIX "Invalid FACS table length: %#x",
facs->length);
goto bad;
}
if (facs->length < 64)
printk(KERN_WARNING PREFIX
"FACS is shorter than ACPI spec allow: 0x%x",
"FACS is shorter than ACPI spec allow: %#x",
facs->length);
acpi_sinfo.wakeup_vector = facs_pa +
xen/arch/x86/acpi/cpu_idle.c
+5 -5
View File
@@ -978,11 +978,11 @@ static void print_cx_pminfo(uint32_t cpu, struct xen_processor_power *power)
return;
printk("\tstates[%d]:\n", i);
printk("\t\treg.space_id = 0x%x\n", state.reg.space_id);
printk("\t\treg.bit_width = 0x%x\n", state.reg.bit_width);
printk("\t\treg.bit_offset = 0x%x\n", state.reg.bit_offset);
printk("\t\treg.access_size = 0x%x\n", state.reg.access_size);
printk("\t\treg.address = 0x%"PRIx64"\n", state.reg.address);
printk("\t\treg.space_id = %#x\n", state.reg.space_id);
printk("\t\treg.bit_width = %#x\n", state.reg.bit_width);
printk("\t\treg.bit_offset = %#x\n", state.reg.bit_offset);
printk("\t\treg.access_size = %#x\n", state.reg.access_size);
printk("\t\treg.address = %#"PRIx64"\n", state.reg.address);
printk("\t\ttype = %d\n", state.type);
printk("\t\tlatency = %d\n", state.latency);
printk("\t\tpower = %d\n", state.power);
xen/arch/x86/apic.c
+2 -2
View File
@@ -689,7 +689,7 @@ void __devinit setup_local_APIC(void)
value = apic_read(APIC_ESR);
if (value != oldvalue)
apic_printk(APIC_VERBOSE, "ESR value before enabling "
"vector: 0x%08lx after: 0x%08lx\n",
"vector: %#lx after: %#lx\n",
oldvalue, value);
} else {
if (esr_disable)
@@ -1210,7 +1210,7 @@ static int __init calibrate_APIC_clock(void)
bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
bus_scale = (1000*262144)/bus_cycle;
apic_printk(APIC_VERBOSE, "..... bus_scale = 0x%08X\n", bus_scale);
apic_printk(APIC_VERBOSE, "..... bus_scale = %#x\n", bus_scale);
/* reset APIC to zero timeout value */
__setup_APIC_LVTT(0);
xen/arch/x86/cpu/mcheck/mce.c
+2 -3
View File
@@ -1147,7 +1147,7 @@ static int x86_mc_msrinject_verify(struct xen_mc_msrinject *mci)
}
if (reason != NULL) {
printk("HV MSR INJECT ERROR: MSR 0x%llx %s\n",
printk("HV MSR INJECT ERROR: MSR %#Lx %s\n",
(unsigned long long)mci->mcinj_msr[i].reg, reason);
errs++;
}
@@ -1191,8 +1191,7 @@ static void x86_mc_msrinject(void *data)
for (i = 0, msr = &mci->mcinj_msr[0];
i < mci->mcinj_count; i++, msr++) {
printk("HV MSR INJECT (%s) target %u actual %u MSR 0x%llx "
"<-- 0x%llx\n",
printk("HV MSR INJECT (%s) target %u actual %u MSR %#Lx <-- %#Lx\n",
intpose ? "interpose" : "hardware",
mci->mcinj_cpunr, smp_processor_id(),
(unsigned long long)msr->reg,
xen/arch/x86/cpu/mcheck/vmce.c
+7 -7
View File
@@ -88,7 +88,7 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
case MSR_IA32_MC0_CTL:
/* stick all 1's to MCi_CTL */
*val = ~0UL;
mce_printk(MCE_VERBOSE, "MCE: rdmsr MC%u_CTL 0x%"PRIx64"\n",
mce_printk(MCE_VERBOSE, "MCE: rdmsr MC%u_CTL %#"PRIx64"\n",
bank, *val);
break;
case MSR_IA32_MC0_STATUS:
@@ -102,7 +102,7 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
*val = entry->mci_status;
mce_printk(MCE_VERBOSE,
"MCE: rd MC%u_STATUS in vMCE# context "
"value 0x%"PRIx64"\n", bank, *val);
"value %#"PRIx64"\n", bank, *val);
}
}
break;
@@ -116,7 +116,7 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
*val = entry->mci_addr;
mce_printk(MCE_VERBOSE,
"MCE: rdmsr MC%u_ADDR in vMCE# context "
"0x%"PRIx64"\n", bank, *val);
"%#"PRIx64"\n", bank, *val);
}
}
break;
@@ -130,7 +130,7 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
*val = entry->mci_misc;
mce_printk(MCE_VERBOSE,
"MCE: rd MC%u_MISC in vMCE# context "
"0x%"PRIx64"\n", bank, *val);
"%#"PRIx64"\n", bank, *val);
}
}
break;
@@ -171,18 +171,18 @@ int vmce_rdmsr(uint32_t msr, uint64_t *val)
*val = vmce->mcg_status;
if (*val)
mce_printk(MCE_VERBOSE,
"MCE: rdmsr MCG_STATUS 0x%"PRIx64"\n", *val);
"MCE: rdmsr MCG_STATUS %#"PRIx64"\n", *val);
break;
case MSR_IA32_MCG_CAP:
*val = cur->arch.mcg_cap;
mce_printk(MCE_VERBOSE, "MCE: rdmsr MCG_CAP 0x%"PRIx64"\n",
mce_printk(MCE_VERBOSE, "MCE: rdmsr MCG_CAP %#"PRIx64"\n",
*val);
break;
case MSR_IA32_MCG_CTL:
/* Stick all 1's when CTL support, and 0's when no CTL support */
if ( cur->arch.mcg_cap & MCG_CTL_P )
*val = ~0ULL;
mce_printk(MCE_VERBOSE, "MCE: rdmsr MCG_CTL 0x%"PRIx64"\n", *val);
mce_printk(MCE_VERBOSE, "MCE: rdmsr MCG_CTL %#"PRIx64"\n", *val);
break;
default:
ret = mce_bank_msr(cur, msr) ? bank_mce_rdmsr(cur, msr, val) : 0;
xen/arch/x86/cpu/mtrr/generic.c
+2 -2
View File
@@ -410,7 +410,7 @@ int generic_validate_add_page(unsigned long base, unsigned long size, unsigned i
boot_cpu_data.x86_model == 1 &&
boot_cpu_data.x86_mask <= 7) {
if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
printk(KERN_WARNING "mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
printk(KERN_WARNING "mtrr: base(%#lx000) is not 4 MiB aligned\n", base);
return -EINVAL;
}
if (!(base + size < 0x70000 || base > 0x7003F) &&
@@ -427,7 +427,7 @@ int generic_validate_add_page(unsigned long base, unsigned long size, unsigned i
for (lbase = base; !(lbase & 1) && (last & 1);
lbase = lbase >> 1, last = last >> 1) ;
if (lbase != last) {
printk(KERN_WARNING "mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n",
printk(KERN_WARNING "mtrr: base(%#lx000) is not aligned on a size(%#lx000) boundary\n",
base, size);
return -EINVAL;
}
xen/arch/x86/cpu/mtrr/main.c
+3 -3
View File
@@ -366,8 +366,8 @@ int mtrr_add_page(unsigned long base, unsigned long size,
continue;
}
printk(KERN_WARNING
"mtrr: 0x%lx000,0x%lx000 overlaps existing"
" 0x%lx000,0x%lx000\n", base, size, lbase,
"mtrr: %#lx000,%#lx000 overlaps existing"
" %#lx000,%#lx000\n", base, size, lbase,
lsize);
goto out;
}
@@ -412,7 +412,7 @@ static int mtrr_check(unsigned long base, unsigned long size)
printk(KERN_WARNING
"mtrr: size and base must be multiples of 4 kiB\n");
printk(KERN_DEBUG
"mtrr: size: 0x%lx base: 0x%lx\n", size, base);
"mtrr: size: %#lx base: %#lx\n", size, base);
dump_stack();
return -1;
}
xen/arch/x86/domain_build.c
+2 -2
View File
@@ -396,13 +396,13 @@ int __init construct_dom0(
}
if (elf_64bit(&elf) && machine == EM_X86_64)
compatible = 1;
printk(" Dom0 kernel: %s%s, %s, paddr 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
printk(" Dom0 kernel: %s%s, %s, paddr %#" PRIx64 " -> %#" PRIx64 "\n",
elf_64bit(&elf) ? "64-bit" : "32-bit",
parms.pae ? ", PAE" : "",
elf_msb(&elf) ? "msb" : "lsb",
elf.pstart, elf.pend);
if ( elf.bsd_symtab_pstart )
printk(" Dom0 symbol map 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
printk(" Dom0 symbol map %#" PRIx64 " -> %#" PRIx64 "\n",
elf.bsd_symtab_pstart, elf.bsd_symtab_pend);
if ( !compatible )
xen/arch/x86/hvm/hvm.c
+3 -3
View File
@@ -1468,7 +1468,7 @@ int hvm_set_efer(uint64_t value)
if ( !hvm_efer_valid(v->domain, value, efer_validbits) )
{
gdprintk(XENLOG_WARNING, "Trying to set reserved bit in "
"EFER: 0x%"PRIx64"\n", value);
"EFER: %#"PRIx64"\n", value);
hvm_inject_hw_exception(TRAP_gp_fault, 0);
return X86EMUL_EXCEPTION;
}
@@ -4095,7 +4095,7 @@ long do_hvm_op(unsigned long op, XEN_GUEST_HANDLE(void) arg)
{
put_gfn(d, pfn);
gdprintk(XENLOG_WARNING,
"type for pfn 0x%lx changed to grant while "
"type for pfn %#lx changed to grant while "
"we were working?\n", pfn);
goto param_fail4;
}
@@ -4106,7 +4106,7 @@ long do_hvm_op(unsigned long op, XEN_GUEST_HANDLE(void) arg)
{
put_gfn(d, pfn);
gdprintk(XENLOG_WARNING,
"type of pfn 0x%lx changed from %d to %d while "
"type of pfn %#lx changed from %d to %d while "
"we were trying to change it to %d\n",
pfn, t, nt, memtype[a.hvmmem_type]);
goto param_fail4;
xen/arch/x86/hvm/io.c
+1 -1
View File
@@ -393,7 +393,7 @@ int dpci_ioport_intercept(ioreq_t *p)
if ( !ioports_access_permitted(d, mport, mport + p->size - 1) )
{
gdprintk(XENLOG_ERR, "Error: access to gport=0x%x denied!\n",
gdprintk(XENLOG_ERR, "Error: access to gport=%#x denied!\n",
(uint32_t)p->addr);
return X86EMUL_UNHANDLEABLE;
}
xen/arch/x86/hvm/irq.c
+1 -1
View File
@@ -488,7 +488,7 @@ static void irq_dump(struct domain *d)
hvm_irq->pci_link_assert_count[1],
hvm_irq->pci_link_assert_count[2],
hvm_irq->pci_link_assert_count[3]);
printk("Callback via %i:0x%"PRIx32",%s asserted\n",
printk("Callback via %i:%#"PRIx32",%s asserted\n",
hvm_irq->callback_via_type, hvm_irq->callback_via.gsi,
hvm_irq->callback_via_asserted ? "" : " not");
}
xen/arch/x86/hvm/svm/intr.c
+1 -1
View File
@@ -175,7 +175,7 @@ void svm_intr_assist(void)
/* Guest already enabled an interrupt window. */
return;
default:
panic("%s: nestedsvm_vcpu_interrupt can't handle value 0x%x\n",
panic("%s: nestedsvm_vcpu_interrupt can't handle value %#x\n",
__func__, rc);
}
}
xen/arch/x86/hvm/svm/nestedsvm.c
+3 -3
View File
@@ -943,7 +943,7 @@ nsvm_vmcb_guest_intercepts_exitcode(struct vcpu *v,
break;
default:
gdprintk(XENLOG_ERR, "Illegal exitcode 0x%"PRIx64"\n", exitcode);
gdprintk(XENLOG_ERR, "Illegal exitcode %#"PRIx64"\n", exitcode);
BUG();
break;
}
@@ -1235,7 +1235,7 @@ int nsvm_wrmsr(struct vcpu *v, unsigned int msr, uint64_t msr_content)
case MSR_K8_VM_HSAVE_PA:
if (!nestedsvm_vmcb_isvalid(v, msr_content)) {
gdprintk(XENLOG_ERR,
"MSR_K8_VM_HSAVE_PA value invalid 0x%"PRIx64"\n", msr_content);
"MSR_K8_VM_HSAVE_PA value invalid %#"PRIx64"\n", msr_content);
ret = -1; /* inject #GP */
break;
}
@@ -1244,7 +1244,7 @@ int nsvm_wrmsr(struct vcpu *v, unsigned int msr, uint64_t msr_content)
case MSR_AMD64_TSC_RATIO:
if ((msr_content & ~TSC_RATIO_RSVD_BITS) != msr_content) {
gdprintk(XENLOG_ERR,
"reserved bits set in MSR_AMD64_TSC_RATIO 0x%"PRIx64"\n",
"reserved bits set in MSR_AMD64_TSC_RATIO %#"PRIx64"\n",
msr_content);
ret = -1; /* inject #GP */
break;
xen/arch/x86/hvm/svm/svm.c
+5 -5
View File
@@ -241,7 +241,7 @@ static int svm_vmcb_restore(struct vcpu *v, struct hvm_hw_cpu *c)
((c->pending_type == 1) || (c->pending_type > 6) ||
(c->pending_reserved != 0)) )
{
gdprintk(XENLOG_ERR, "Invalid pending event 0x%"PRIx32".\n",
gdprintk(XENLOG_ERR, "Invalid pending event %#"PRIx32".\n",
c->pending_event);
return -EINVAL;
}
@@ -254,7 +254,7 @@ static int svm_vmcb_restore(struct vcpu *v, struct hvm_hw_cpu *c)
NULL, P2M_ALLOC);
if ( !page )
{
gdprintk(XENLOG_ERR, "Invalid CR3 value=0x%"PRIx64"\n",
gdprintk(XENLOG_ERR, "Invalid CR3 value=%#"PRIx64"\n",
c->cr3);
return -EINVAL;
}
@@ -289,7 +289,7 @@ static int svm_vmcb_restore(struct vcpu *v, struct hvm_hw_cpu *c)
if ( c->pending_valid )
{
gdprintk(XENLOG_INFO, "Re-injecting 0x%"PRIx32", 0x%"PRIx32"\n",
gdprintk(XENLOG_INFO, "Re-injecting %#"PRIx32", %#"PRIx32"\n",
c->pending_event, c->error_code);
if ( hvm_event_needs_reinjection(c->pending_type, c->pending_vector) )
@@ -2398,8 +2398,8 @@ void svm_vmexit_handler(struct cpu_user_regs *regs)
default:
exit_and_crash:
gdprintk(XENLOG_ERR, "unexpected VMEXIT: exit reason = 0x%"PRIx64", "
"exitinfo1 = %"PRIx64", exitinfo2 = %"PRIx64"\n",
gdprintk(XENLOG_ERR, "unexpected VMEXIT: exit reason = %#"PRIx64", "
"exitinfo1 = %#"PRIx64", exitinfo2 = %#"PRIx64"\n",
exit_reason,
(u64)vmcb->exitinfo1, (u64)vmcb->exitinfo2);
domain_crash(v->domain);
xen/arch/x86/hvm/svm/svmdebug.c
+24 -25
View File
@@ -32,33 +32,32 @@ static void svm_dump_sel(const char *name, svm_segment_register_t *s)
void svm_vmcb_dump(const char *from, struct vmcb_struct *vmcb)
{
printk("Dumping guest's current state at %s...\n", from);
printk("Size of VMCB = %d, paddr = 0x%016lx, vaddr = %p\n",
printk("Size of VMCB = %d, paddr = %#lx, vaddr = %p\n",
(int) sizeof(struct vmcb_struct), virt_to_maddr(vmcb), vmcb);
printk("cr_intercepts = 0x%08x dr_intercepts = 0x%08x "
"exception_intercepts = 0x%08x\n",
printk("cr_intercepts = %#x dr_intercepts = %#x "
"exception_intercepts = %#x\n",
vmcb->_cr_intercepts, vmcb->_dr_intercepts,
vmcb->_exception_intercepts);
printk("general1_intercepts = 0x%08x general2_intercepts = 0x%08x\n",
printk("general1_intercepts = %#x general2_intercepts = %#x\n",
vmcb->_general1_intercepts, vmcb->_general2_intercepts);
printk("iopm_base_pa = 0x%016llx msrpm_base_pa = 0x%016llx tsc_offset = "
"0x%016llx\n",
printk("iopm_base_pa = %#Lx msrpm_base_pa = %#Lx tsc_offset = %#Lx\n",
(unsigned long long)vmcb->_iopm_base_pa,
(unsigned long long)vmcb->_msrpm_base_pa,
(unsigned long long)vmcb->_tsc_offset);
printk("tlb_control = 0x%08x vintr = 0x%016llx interrupt_shadow = "
"0x%016llx\n", vmcb->tlb_control,
printk("tlb_control = %#x vintr = %#Lx interrupt_shadow = %#Lx\n",
vmcb->tlb_control,
(unsigned long long)vmcb->_vintr.bytes,
(unsigned long long)vmcb->interrupt_shadow);
printk("exitcode = 0x%016llx exitintinfo = 0x%016llx\n",
printk("exitcode = %#Lx exitintinfo = %#Lx\n",
(unsigned long long)vmcb->exitcode,
(unsigned long long)vmcb->exitintinfo.bytes);
printk("exitinfo1 = 0x%016llx exitinfo2 = 0x%016llx \n",
printk("exitinfo1 = %#Lx exitinfo2 = %#Lx \n",
(unsigned long long)vmcb->exitinfo1,
(unsigned long long)vmcb->exitinfo2);
printk("np_enable = 0x%016llx guest_asid = 0x%03x\n",
printk("np_enable = %Lx guest_asid = %#x\n",
(unsigned long long)vmcb->_np_enable, vmcb->_guest_asid);
printk("cpl = %d efer = 0x%016llx star = 0x%016llx lstar = 0x%016llx\n",
printk("cpl = %d efer = %#Lx star = %#Lx lstar = %#Lx\n",
vmcb->_cpl, (unsigned long long)vmcb->_efer,
(unsigned long long)vmcb->star, (unsigned long long)vmcb->lstar);
printk("CR0 = 0x%016llx CR2 = 0x%016llx\n",
@@ -77,7 +76,7 @@ void svm_vmcb_dump(const char *from, struct vmcb_struct *vmcb)
printk("KernGSBase = 0x%016llx PAT = 0x%016llx \n",
(unsigned long long)vmcb->kerngsbase,
(unsigned long long)vmcb->_g_pat);
printk("H_CR3 = 0x%016llx CleanBits = 0x%08x\n",
printk("H_CR3 = 0x%016llx CleanBits = %#x\n",
(unsigned long long)vmcb->_h_cr3, vmcb->cleanbits.bytes);
/* print out all the selectors */
@@ -104,48 +103,48 @@ svm_vmcb_isvalid(const char *from, struct vmcb_struct *vmcb,
} else return 1;
if ((vmcb->_efer & EFER_SVME) == 0) {
PRINTF("EFER: SVME bit not set (0x%"PRIx64")\n", vmcb->_efer);
PRINTF("EFER: SVME bit not set (%#"PRIx64")\n", vmcb->_efer);
}
if ((vmcb->_cr0 & X86_CR0_CD) == 0 && (vmcb->_cr0 & X86_CR0_NW) != 0) {
PRINTF("CR0: CD bit is zero and NW bit set (0x%"PRIx64")\n",
PRINTF("CR0: CD bit is zero and NW bit set (%#"PRIx64")\n",
vmcb->_cr0);
}
if ((vmcb->_cr0 >> 32U) != 0) {
PRINTF("CR0: bits [63:32] are not zero (0x%"PRIx64")\n",
PRINTF("CR0: bits [63:32] are not zero (%#"PRIx64")\n",
vmcb->_cr0);
}
if ((vmcb->_cr3 & 0x7) != 0) {
PRINTF("CR3: MBZ bits are set (0x%"PRIx64")\n", vmcb->_cr3);
PRINTF("CR3: MBZ bits are set (%#"PRIx64")\n", vmcb->_cr3);
}
if ((vmcb->_efer & EFER_LMA) && (vmcb->_cr3 & 0xfe) != 0) {
PRINTF("CR3: MBZ bits are set (0x%"PRIx64")\n", vmcb->_cr3);
PRINTF("CR3: MBZ bits are set (%#"PRIx64")\n", vmcb->_cr3);
}
if ((vmcb->_cr4 >> 19U) != 0) {
PRINTF("CR4: bits [63:19] are not zero (0x%"PRIx64")\n",
PRINTF("CR4: bits [63:19] are not zero (%#"PRIx64")\n",
vmcb->_cr4);
}
if (((vmcb->_cr4 >> 11U) & 0x7fU) != 0) {
PRINTF("CR4: bits [17:11] are not zero (0x%"PRIx64")\n",
PRINTF("CR4: bits [17:11] are not zero (%#"PRIx64")\n",
vmcb->_cr4);
}
if ((vmcb->_dr6 >> 32U) != 0) {
PRINTF("DR6: bits [63:32] are not zero (0x%"PRIx64")\n",
PRINTF("DR6: bits [63:32] are not zero (%#"PRIx64")\n",
vmcb->_dr6);
}
if ((vmcb->_dr7 >> 32U) != 0) {
PRINTF("DR7: bits [63:32] are not zero (0x%"PRIx64")\n",
PRINTF("DR7: bits [63:32] are not zero (%#"PRIx64")\n",
vmcb->_dr7);
}
if ((vmcb->_efer >> 15U) != 0) {
PRINTF("EFER: bits [63:15] are not zero (0x%"PRIx64")\n",
PRINTF("EFER: bits [63:15] are not zero (%#"PRIx64")\n",
vmcb->_efer);
}
@@ -168,12 +167,12 @@ svm_vmcb_isvalid(const char *from, struct vmcb_struct *vmcb,
}
if ((vmcb->_general2_intercepts & GENERAL2_INTERCEPT_VMRUN) == 0) {
PRINTF("GENERAL2_INTERCEPT: VMRUN intercept bit is clear (0x%"PRIx32")\n",
PRINTF("GENERAL2_INTERCEPT: VMRUN intercept bit is clear (%#"PRIx32")\n",
vmcb->_general2_intercepts);
}
if (vmcb->eventinj.fields.resvd1 != 0) {
PRINTF("eventinj: MBZ bits are set (0x%"PRIx64")\n",
PRINTF("eventinj: MBZ bits are set (%#"PRIx64")\n",
vmcb->eventinj.bytes);
}
xen/arch/x86/hvm/vlapic.c
+11 -11
View File
@@ -172,7 +172,7 @@ static uint32_t vlapic_get_ppr(struct vlapic *vlapic)
ppr = isrv & 0xf0;
HVM_DBG_LOG(DBG_LEVEL_VLAPIC_INTERRUPT,
"vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
"vlapic %p, ppr %#x, isr %#x, isrv %#x",
vlapic, ppr, isr, isrv);
return ppr;
@@ -215,8 +215,8 @@ bool_t vlapic_match_dest(
struct vlapic *target, struct vlapic *source,
int short_hand, uint8_t dest, uint8_t dest_mode)
{
HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "target %p, source %p, dest 0x%x, "
"dest_mode 0x%x, short_hand 0x%x",
HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "target %p, source %p, dest %#x, "
"dest_mode %#x, short_hand %#x",
target, source, dest, dest_mode, short_hand);
switch ( short_hand )
@@ -562,20 +562,20 @@ static int vlapic_read(
break;
default:
gdprintk(XENLOG_ERR, "Local APIC read with len=0x%lx, "
gdprintk(XENLOG_ERR, "Local APIC read with len=%#lx, "
"should be 4 instead.\n", len);
goto exit_and_crash;
}
HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "offset 0x%x with length 0x%lx, "
"and the result is 0x%lx", offset, len, result);
HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "offset %#x with length %#lx, "
"and the result is %#lx", offset, len, result);
out:
*pval = result;
return X86EMUL_OKAY;
unaligned_exit_and_crash:
gdprintk(XENLOG_ERR, "Unaligned LAPIC read len=0x%lx at offset=0x%x.\n",
gdprintk(XENLOG_ERR, "Unaligned LAPIC read len=%#lx at offset=%#x.\n",
len, offset);
exit_and_crash:
domain_crash(v->domain);
@@ -759,7 +759,7 @@ static int vlapic_reg_write(struct vcpu *v,
case APIC_TDCR:
vlapic_set_tdcr(vlapic, val & 0xb);
HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER, "timer divisor is 0x%x",
HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER, "timer divisor is %#x",
vlapic->hw.timer_divisor);
break;
@@ -768,7 +768,7 @@ static int vlapic_reg_write(struct vcpu *v,
}
if (rc == X86EMUL_UNHANDLEABLE)
gdprintk(XENLOG_DEBUG,
"Local APIC Write wrong to register 0x%x\n", offset);
"Local APIC Write wrong to register %#x\n", offset);
return rc;
}
@@ -781,7 +781,7 @@ static int vlapic_write(struct vcpu *v, unsigned long address,
if ( offset != 0xb0 )
HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
"offset 0x%x with length 0x%lx, and value is 0x%lx",
"offset %#x with length %#lx, and value is %#lx",
offset, len, val);
/*
@@ -827,7 +827,7 @@ static int vlapic_write(struct vcpu *v, unsigned long address,
return vlapic_reg_write(v, offset, val);
unaligned_exit_and_crash:
gdprintk(XENLOG_ERR, "Unaligned LAPIC write len=0x%lx at offset=0x%x.\n",
gdprintk(XENLOG_ERR, "Unaligned LAPIC write len=%#lx at offset=%#x.\n",
len, offset);
exit_and_crash:
domain_crash(v->domain);
xen/arch/x86/hvm/vmx/vmcs.c
+1 -1
View File
@@ -121,7 +121,7 @@ static u32 adjust_vmx_controls(
static bool_t cap_check(const char *name, u32 expected, u32 saw)
{
if ( saw != expected )
printk("VMX %s: saw 0x%08x expected 0x%08x\n", name, saw, expected);
printk("VMX %s: saw %#x expected %#x\n", name, saw, expected);
return saw != expected;
}
xen/arch/x86/hvm/vmx/vmx.c
+9 -10
View File
@@ -210,7 +210,7 @@ long_mode_do_msr_read(unsigned int msr, uint64_t *msr_content)
return HNDL_unhandled;
}
HVM_DBG_LOG(DBG_LEVEL_0, "msr 0x%x content 0x%"PRIx64, msr, *msr_content);
HVM_DBG_LOG(DBG_LEVEL_0, "msr %#x content %#"PRIx64, msr, *msr_content);
return HNDL_done;
}
@@ -222,7 +222,7 @@ long_mode_do_msr_write(unsigned int msr, uint64_t msr_content)
struct vmx_msr_state *guest_msr_state = &v->arch.hvm_vmx.msr_state;
struct vmx_msr_state *host_msr_state = &this_cpu(host_msr_state);
HVM_DBG_LOG(DBG_LEVEL_0, "msr 0x%x content 0x%"PRIx64, msr, msr_content);
HVM_DBG_LOG(DBG_LEVEL_0, "msr %#x content %#"PRIx64, msr, msr_content);
switch ( msr )
{
@@ -466,7 +466,7 @@ static int vmx_restore_cr0_cr3(
NULL, P2M_ALLOC);
if ( !page )
{
gdprintk(XENLOG_ERR, "Invalid CR3 value=0x%lx\n", cr3);
gdprintk(XENLOG_ERR, "Invalid CR3 value=%#lx\n", cr3);
return -EINVAL;
}
}
@@ -492,7 +492,7 @@ static int vmx_vmcs_restore(struct vcpu *v, struct hvm_hw_cpu *c)
((c->pending_type == 1) || (c->pending_type > 6) ||
(c->pending_reserved != 0)) )
{
gdprintk(XENLOG_ERR, "Invalid pending event 0x%"PRIx32".\n",
gdprintk(XENLOG_ERR, "Invalid pending event %#"PRIx32".\n",
c->pending_event);
return -EINVAL;
}
@@ -524,7 +524,7 @@ static int vmx_vmcs_restore(struct vcpu *v, struct hvm_hw_cpu *c)
if ( c->pending_valid )
{
gdprintk(XENLOG_INFO, "Re-injecting 0x%"PRIx32", 0x%"PRIx32"\n",
gdprintk(XENLOG_INFO, "Re-injecting %#"PRIx32", %#"PRIx32"\n",
c->pending_event, c->error_code);
if ( hvm_event_needs_reinjection(c->pending_type, c->pending_vector) )
@@ -1789,7 +1789,7 @@ static int is_last_branch_msr(u32 ecx)
static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content)
{
HVM_DBG_LOG(DBG_LEVEL_1, "ecx=%x", msr);
HVM_DBG_LOG(DBG_LEVEL_1, "ecx=%#x", msr);
switch ( msr )
{
@@ -1854,7 +1854,7 @@ static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content)
}
done:
HVM_DBG_LOG(DBG_LEVEL_1, "returns: ecx=%x, msr_value=0x%"PRIx64,
HVM_DBG_LOG(DBG_LEVEL_1, "returns: ecx=%#x, msr_value=%#"PRIx64,
msr, *msr_content);
return X86EMUL_OKAY;
@@ -1927,8 +1927,7 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content)
{
struct vcpu *v = current;
HVM_DBG_LOG(DBG_LEVEL_1, "ecx=%x, msr_value=0x%"PRIx64,
msr, msr_content);
HVM_DBG_LOG(DBG_LEVEL_1, "ecx=%#x, msr_value=%#"PRIx64, msr, msr_content);
switch ( msr )
{
@@ -2107,7 +2106,7 @@ static void vmx_failed_vmentry(unsigned int exit_reason,
unsigned long exit_qualification = __vmread(EXIT_QUALIFICATION);
struct vcpu *curr = current;
printk("Failed vm entry (exit reason 0x%x) ", exit_reason);
printk("Failed vm entry (exit reason %#x) ", exit_reason);
switch ( failed_vmentry_reason )
{
case EXIT_REASON_INVALID_GUEST_STATE:
xen/arch/x86/io_apic.c
+1 -1
View File
@@ -2204,7 +2204,7 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int a
entry.vector = vector;
apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
"(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
"(%d-%d -> %#x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
edge_level, active_high_low);
xen/arch/x86/microcode_amd.c
+3 -3
View File
@@ -88,7 +88,7 @@ static int collect_cpu_info(int cpu, struct cpu_signature *csig)
rdmsrl(MSR_AMD_PATCHLEVEL, csig->rev);
printk(KERN_DEBUG "microcode: collect_cpu_info: patch_id=0x%x\n",
printk(KERN_DEBUG "microcode: collect_cpu_info: patch_id=%#x\n",
csig->rev);
return 0;
@@ -132,7 +132,7 @@ static int microcode_fits(const struct microcode_amd *mc_amd, int cpu)
return 0;
printk(KERN_DEBUG "microcode: CPU%d found a matching microcode "
"update with version 0x%x (current=0x%x)\n",
"update with version %#x (current=%#x)\n",
cpu, mc_header->patch_id, uci->cpu_sig.rev);
return 1;
@@ -169,7 +169,7 @@ static int apply_microcode(int cpu)
if ( rev != hdr->patch_id )
{
printk(KERN_ERR "microcode: CPU%d update from revision "
"0x%x to 0x%x failed\n", cpu, hdr->patch_id, rev);
"%#x to %#x failed\n", cpu, hdr->patch_id, rev);
return -EIO;
}
xen/arch/x86/microcode_intel.c
+4 -4
View File
@@ -122,7 +122,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
/* get the current revision from MSR 0x8B */
rdmsrl(MSR_IA32_UCODE_REV, msr_content);
csig->rev = (uint32_t)(msr_content >> 32);
pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n",
pr_debug("microcode: collect_cpu_info : sig=%#x, pf=%#x, rev=%#x\n",
csig->sig, csig->pf, csig->rev);
return 0;
@@ -264,7 +264,7 @@ static int get_matching_microcode(const void *mc, int cpu)
if ( uci->mc.mc_intel && uci->mc.mc_intel->hdr.rev >= mc_header->rev )
return 0;
pr_debug("microcode: CPU%d found a matching microcode update with"
" version 0x%x (current=0x%x)\n",
" version %#x (current=%#x)\n",
cpu, mc_header->rev, uci->cpu_sig.rev);
new_mc = xmalloc_bytes(total_size);
if ( new_mc == NULL )
@@ -311,11 +311,11 @@ static int apply_microcode(int cpu)
if ( val[1] != uci->mc.mc_intel->hdr.rev )
{
printk(KERN_ERR "microcode: CPU%d update from revision "
"0x%x to 0x%x failed\n", cpu_num, uci->cpu_sig.rev, val[1]);
"%#x to %#x failed\n", cpu_num, uci->cpu_sig.rev, val[1]);
return -EIO;
}
printk(KERN_INFO "microcode: CPU%d updated from revision "
"0x%x to 0x%x, date = %04x-%02x-%02x \n",
"%#x to %#x, date = %04x-%02x-%02x \n",
cpu_num, uci->cpu_sig.rev, val[1],
uci->mc.mc_intel->hdr.date & 0xffff,
uci->mc.mc_intel->hdr.date >> 24,
xen/arch/x86/mm.c
+1 -1
View File
@@ -3102,7 +3102,7 @@ long do_mmuext_op(
}
default:
MEM_LOG("Invalid extended pt command 0x%x", op.cmd);
MEM_LOG("Invalid extended pt command %#x", op.cmd);
rc = -ENOSYS;
okay = 0;
break;
xen/arch/x86/mm/hap/nested_hap.c
+1 -1
View File
@@ -129,7 +129,7 @@ nestedhap_fix_p2m(struct vcpu *v, struct p2m_domain *p2m,
if (rv == 0) {
gdprintk(XENLOG_ERR,
"failed to set entry for 0x%"PRIx64" -> 0x%"PRIx64"\n",
"failed to set entry for %#"PRIx64" -> %#"PRIx64"\n",
L2_gpa, L0_gpa);
BUG();
}
xen/arch/x86/mm/p2m-pt.c
+2 -2
View File
@@ -110,8 +110,8 @@ p2m_find_entry(void *table, unsigned long *gfn_remainder,
index = *gfn_remainder >> shift;
if ( index >= max )
{
P2M_DEBUG("gfn=0x%lx out of range "
"(gfn_remainder=0x%lx shift=%d index=0x%x max=0x%x)\n",
P2M_DEBUG("gfn=%#lx out of range "
"(gfn_remainder=%#lx shift=%d index=%#x max=%#x)\n",
gfn, *gfn_remainder, shift, index, max);
return NULL;
}
xen/arch/x86/mm/shadow/common.c
+3 -3
View File
@@ -872,7 +872,7 @@ static int sh_skip_sync(struct vcpu *v, mfn_t gl1mfn)
return SHADOW_INTERNAL_NAME(sh_safe_not_to_sync, 3)(v, gl1mfn);
else if ( pg->shadow_flags & SHF_L1_64 )
return SHADOW_INTERNAL_NAME(sh_safe_not_to_sync, 4)(v, gl1mfn);
SHADOW_ERROR("gmfn 0x%lx was OOS but not shadowed as an l1.\n",
SHADOW_ERROR("gmfn %#lx was OOS but not shadowed as an l1.\n",
mfn_x(gl1mfn));
BUG();
return 0; /* BUG() is no longer __attribute__((noreturn)). */
@@ -2596,8 +2596,8 @@ void sh_remove_shadows(struct vcpu *v, mfn_t gmfn, int fast, int all)
smfn = shadow_hash_lookup(v, mfn_x(gmfn), t); \
if ( unlikely(!mfn_valid(smfn)) ) \
{ \
SHADOW_ERROR(": gmfn %#lx has flags 0x%"PRIx32 \
" but no type-0x%"PRIx32" shadow\n", \
SHADOW_ERROR(": gmfn %#lx has flags %#"PRIx32 \
" but no type-%#"PRIx32" shadow\n", \
mfn_x(gmfn), (uint32_t)pg->shadow_flags, t); \
break; \
} \
xen/arch/x86/mm/shadow/multi.c
+1 -1
View File
@@ -2171,7 +2171,7 @@ static int validate_gl4e(struct vcpu *v, void *new_ge, mfn_t sl4mfn, void *se)
// attempt by the guest to write to a xen reserved slot
//
SHADOW_PRINTK("%s out-of-range update "
"sl4mfn=%05lx index=0x%x val=%" SH_PRI_pte "\n",
"sl4mfn=%05lx index=%#x val=%" SH_PRI_pte "\n",
__func__, mfn_x(sl4mfn), shadow_index, new_sl4e.l4);
if ( shadow_l4e_get_flags(new_sl4e) & _PAGE_PRESENT )
{
xen/arch/x86/mpparse.c
+4 -4
View File
@@ -216,7 +216,7 @@ static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
if (!(m->mpc_flags & MPC_APIC_USABLE))
return;
printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
printk(KERN_INFO "I/O APIC #%d Version %d at %#x.\n",
m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
if (nr_ioapics >= MAX_IO_APICS) {
printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
@@ -278,7 +278,7 @@ static int __init smp_read_mpc(struct mp_config_table *mpc)
unsigned char *mpt=((unsigned char *)mpc)+count;
if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
printk(KERN_ERR "SMP mptable: bad signature [%#x]!\n",
*(u32 *)mpc->mpc_signature);
return 0;
}
@@ -305,7 +305,7 @@ static int __init smp_read_mpc(struct mp_config_table *mpc)
mps_oem_check(mpc, oem, str);
printk("APIC at: 0x%X\n",mpc->mpc_lapic);
printk("APIC at: %#x\n", mpc->mpc_lapic);
/*
* Save the local APIC address (it might be non-default) -- but only
@@ -881,7 +881,7 @@ void __init mp_register_ioapic (
mp_ioapic_routing[idx].gsi_end = gsi_base +
io_apic_get_redir_entries(idx);
printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
printk("IOAPIC[%d]: apic_id %d, version %d, address %#x, "
"GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
mp_ioapic_routing[idx].gsi_base,
xen/arch/x86/nmi.c
+1 -1
View File
@@ -245,7 +245,7 @@ static inline void write_watchdog_counter(const char *descr)
do_div(count, nmi_hz);
if(descr)
Dprintk("setting %s to -0x%"PRIx64"\n", descr, count);
Dprintk("setting %s to -%#"PRIx64"\n", descr, count);
wrmsrl(nmi_perfctr_msr, 0 - count);
}
xen/arch/x86/oprofile/op_model_athlon.c
+2 -2
View File
@@ -478,7 +478,7 @@ static int __init init_ibs_nmi(void)
if (value != (IBSCTL_LVTOFFSETVAL |
APIC_EILVT_LVTOFF_IBS)) {
printk("Xenoprofile: Failed to setup IBS LVT offset, "
"IBSCTL = %#08x\n", value);
"IBSCTL = %#x\n", value);
return 1;
}
nodes++;
@@ -523,7 +523,7 @@ void __init ibs_init(void)
return;
}
printk("Xenoprofile: AMD IBS detected (0x%08x)\n",
printk("Xenoprofile: AMD IBS detected (%#x)\n",
(unsigned)ibs_caps);
}
xen/arch/x86/oprofile/op_model_p4.c
+2 -3
View File
@@ -485,8 +485,7 @@ static void pmc_setup_one_p4_counter(unsigned int ctr)
/* find our event binding structure. */
if (counter_config[ctr].event <= 0 || counter_config[ctr].event > NUM_EVENTS) {
printk(KERN_ERR
"oprofile: P4 event code 0x%lx out of range\n",
printk(KERN_ERR "oprofile: P4 event code %#lx out of range\n",
counter_config[ctr].event);
return;
}
@@ -526,7 +525,7 @@ static void pmc_setup_one_p4_counter(unsigned int ctr)
}
printk(KERN_ERR
"oprofile: P4 event code 0x%lx no binding, stag %d ctr %d\n",
"oprofile: P4 event code %#lx no binding, stag %d ctr %d\n",
counter_config[ctr].event, stag, ctr);
}
xen/arch/x86/setup.c
+2 -2
View File
@@ -482,13 +482,13 @@ static void __init kexec_reserve_area(struct e820map *e820)
if ( !reserve_e820_ram(e820, kdump_start, kdump_start + kdump_size) )
{
printk("Kdump: DISABLED (failed to reserve %luMB (%lukB) at 0x%lx)"
printk("Kdump: DISABLED (failed to reserve %luMB (%lukB) at %#lx)"
"\n", kdump_size >> 20, kdump_size >> 10, kdump_start);
kexec_crash_area.start = kexec_crash_area.size = 0;
}
else
{
printk("Kdump: %luMB (%lukB) at 0x%lx\n",
printk("Kdump: %luMB (%lukB) at %#lx\n",
kdump_size >> 20, kdump_size >> 10, kdump_start);
}
}
xen/arch/x86/tboot.c
+6 -6
View File
@@ -119,12 +119,12 @@ void __init tboot_probe(void)
g_tboot_shared = tboot_shared;
printk("TBOOT: found shared page at phys addr %lx:\n", p_tboot_shared);
printk(" version: %d\n", tboot_shared->version);
printk(" log_addr: 0x%08x\n", tboot_shared->log_addr);
printk(" shutdown_entry: 0x%08x\n", tboot_shared->shutdown_entry);
printk(" tboot_base: 0x%08x\n", tboot_shared->tboot_base);
printk(" tboot_size: 0x%x\n", tboot_shared->tboot_size);
printk(" log_addr: %#x\n", tboot_shared->log_addr);
printk(" shutdown_entry: %#x\n", tboot_shared->shutdown_entry);
printk(" tboot_base: %#x\n", tboot_shared->tboot_base);
printk(" tboot_size: %#x\n", tboot_shared->tboot_size);
if ( tboot_shared->version >= 6 )
printk(" flags: 0x%08x\n", tboot_shared->flags);
printk(" flags: %#x\n", tboot_shared->flags);
/* these will be needed by tboot_protect_mem_regions() and/or
tboot_parse_dmar_table(), so get them now */
@@ -352,7 +352,7 @@ void tboot_shutdown(uint32_t shutdown_type)
__PAGE_HYPERVISOR);
if ( err != 0 )
{
printk("error (0x%x) mapping tboot pages (mfns) @ 0x%x, 0x%x\n", err,
printk("error (%#x) mapping tboot pages (mfns) @ %#x, %#x\n", err,
map_base, map_size);
return;
}
xen/arch/x86/time.c
+3 -3
View File
@@ -1955,11 +1955,11 @@ static void dump_softtsc(unsigned char key)
printk("dom%u%s: mode=%d",d->domain_id,
is_hvm_domain(d) ? "(hvm)" : "", d->arch.tsc_mode);
if ( d->arch.vtsc_offset )
printk(",ofs=0x%"PRIx64"",d->arch.vtsc_offset);
printk(",ofs=%#"PRIx64, d->arch.vtsc_offset);
if ( d->arch.tsc_khz )
printk(",khz=%"PRIu32"",d->arch.tsc_khz);
printk(",khz=%"PRIu32, d->arch.tsc_khz);
if ( d->arch.incarnation )
printk(",inc=%"PRIu32"",d->arch.incarnation);
printk(",inc=%"PRIu32, d->arch.incarnation);
if ( !(d->arch.vtsc_kerncount | d->arch.vtsc_usercount) )
{
printk("\n");
xen/arch/x86/xstate.c
+1 -1
View File
@@ -163,7 +163,7 @@ void xstate_init(void)
xsave_cntxt_size = ebx;
xfeature_mask = eax + ((u64)edx << 32);
xfeature_mask &= XCNTXT_MASK;
printk("%s: using cntxt_size: 0x%x and states: 0x%"PRIx64"\n",
printk("%s: using cntxt_size: %#x and states: %#"PRIx64"\n",
__func__, xsave_cntxt_size, xfeature_mask);
/* Check XSAVEOPT feature. */
xen/common/gdbstub.c
+1 -1
View File
@@ -263,7 +263,7 @@ gdb_write_to_packet_hex(unsigned long x, int int_size, struct gdb_context *ctx)
case sizeof(u64):
break;
default:
dbg_printk("WARNING: %s x: 0x%lx int_size: %d\n",
dbg_printk("WARNING: %s x: %#lx int_size: %d\n",
__func__, x, int_size);
break;
}
xen/common/page_alloc.c
+1 -1
View File
@@ -367,7 +367,7 @@ static void __init setup_low_mem_virq(void)
low_mem_virq_th = low_mem_virq_orig = 1UL << order;
low_mem_virq_th_order = order;
printk("Initial low memory virq threshold set at 0x%lx pages.\n",
printk("Initial low memory virq threshold set at %#lx pages.\n",
low_mem_virq_th);
}
xen/common/vsprintf.c
+9 -9
View File
@@ -171,10 +171,14 @@ static char *number(
}
}
if (type & SPECIAL) {
if (base == 16)
if (num == 0)
type &= ~SPECIAL;
else if (base == 16)
size -= 2;
else if (base == 8)
size--;
else
type &= ~SPECIAL;
}
i = 0;
if (num == 0)
@@ -197,14 +201,10 @@ static char *number(
++buf;
}
if (type & SPECIAL) {
if (base==8) {
if (buf <= end)
*buf = '0';
++buf;
} else if (base==16) {
if (buf <= end)
*buf = '0';
++buf;
if (buf <= end)
*buf = '0';
++buf;
if (base == 16) {
if (buf <= end)
*buf = digits[33];
++buf;
xen/common/xencomm.c
+2 -2
View File
@@ -58,7 +58,7 @@ xencomm_get_page(unsigned long paddr, struct page_info **page)
* is freed with decrease reservation hypercall at the same time.
*/
gdprintk(XENLOG_WARNING,
"bad page is passed. paddr 0x%lx maddr 0x%lx\n",
"bad page is passed. paddr %#lx maddr %#lx\n",
paddr, maddr);
return -EFAULT;
}
@@ -117,7 +117,7 @@ xencomm_ctxt_init(const void *handle, struct xencomm_ctxt *ctxt)
desc = xencomm_vaddr((unsigned long)handle, page);
if ( desc->magic != XENCOMM_MAGIC )
{
printk("%s: error: %p magic was 0x%x\n", __func__, desc, desc->magic);
printk("%s: error: %p magic was %#x\n", __func__, desc, desc->magic);
put_page(page);
return -EINVAL;
}
xen/drivers/acpi/numa.c
+3 -3
View File
@@ -78,8 +78,8 @@ void __init acpi_table_print_srat_entry(struct acpi_subtable_header * header)
if (srat_rev < 2)
proximity_domain &= 0xff;
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"SRAT Memory (%#016"PRIx64
" length %#016"PRIx64")"
"SRAT Memory (%#"PRIx64
" length %#"PRIx64")"
" in proximity domain %d %s%s\n",
p->base_address, p->length,
proximity_domain,
@@ -108,7 +108,7 @@ void __init acpi_table_print_srat_entry(struct acpi_subtable_header * header)
break;
default:
printk(KERN_WARNING PREFIX
"Found unsupported SRAT entry (type = 0x%x)\n",
"Found unsupported SRAT entry (type = %#x)\n",
header->type);
break;
}
xen/drivers/acpi/tables.c
+7 -7
View File
@@ -95,7 +95,7 @@ void __init acpi_table_print_madt_entry(struct acpi_subtable_header *header)
if (p->inti_flags &
~(ACPI_MADT_POLARITY_MASK | ACPI_MADT_TRIGGER_MASK))
printk(KERN_INFO PREFIX
"INT_SRC_OVR unexpected reserved flags: 0x%x\n",
"INT_SRC_OVR unexpected reserved flags: %#x\n",
p->inti_flags &
~(ACPI_MADT_POLARITY_MASK | ACPI_MADT_TRIGGER_MASK));
@@ -119,7 +119,7 @@ void __init acpi_table_print_madt_entry(struct acpi_subtable_header *header)
struct acpi_madt_local_apic_nmi *p =
(struct acpi_madt_local_apic_nmi *)header;
printk(KERN_INFO PREFIX
"LAPIC_NMI (acpi_id[0x%02x] %s %s lint[0x%x])\n",
"LAPIC_NMI (acpi_id[0x%02x] %s %s lint[%#x])\n",
p->processor_id,
mps_inti_flags_polarity[p->inti_flags & ACPI_MADT_POLARITY_MASK ],
mps_inti_flags_trigger[(p->inti_flags & ACPI_MADT_TRIGGER_MASK) >> 2],
@@ -137,7 +137,7 @@ void __init acpi_table_print_madt_entry(struct acpi_subtable_header *header)
trigger = (p->inti_flags & ACPI_MADT_TRIGGER_MASK) >> 2;
printk(KERN_INFO PREFIX
"X2APIC_NMI (uid[0x%02x] %s %s lint[0x%x])\n",
"X2APIC_NMI (uid[0x%02x] %s %s lint[%#x])\n",
p->uid,
mps_inti_flags_polarity[polarity],
mps_inti_flags_trigger[trigger],
@@ -160,7 +160,7 @@ void __init acpi_table_print_madt_entry(struct acpi_subtable_header *header)
struct acpi_madt_io_sapic *p =
(struct acpi_madt_io_sapic *)header;
printk(KERN_INFO PREFIX
"IOSAPIC (id[0x%x] address[%p] gsi_base[%d])\n",
"IOSAPIC (id[%#x] address[%p] gsi_base[%d])\n",
p->id, (void *)(unsigned long)p->address,
p->global_irq_base);
}
@@ -182,7 +182,7 @@ void __init acpi_table_print_madt_entry(struct acpi_subtable_header *header)
struct acpi_madt_interrupt_source *p =
(struct acpi_madt_interrupt_source *)header;
printk(KERN_INFO PREFIX
"PLAT_INT_SRC (%s %s type[0x%x] id[0x%04x] eid[0x%x] iosapic_vector[0x%x] global_irq[0x%x]\n",
"PLAT_INT_SRC (%s %s type[%#x] id[0x%04x] eid[%#x] iosapic_vector[%#x] global_irq[%#x]\n",
mps_inti_flags_polarity[p->inti_flags & ACPI_MADT_POLARITY_MASK],
mps_inti_flags_trigger[(p->inti_flags & ACPI_MADT_TRIGGER_MASK) >> 2],
p->type, p->id, p->eid, p->io_sapic_vector,
@@ -192,7 +192,7 @@ void __init acpi_table_print_madt_entry(struct acpi_subtable_header *header)
default:
printk(KERN_WARNING PREFIX
"Found unsupported MADT entry (type = 0x%x)\n",
"Found unsupported MADT entry (type = %#x)\n",
header->type);
break;
}
@@ -242,7 +242,7 @@ acpi_table_parse_entries(char *id,
((unsigned long)entry + entry->length);
}
if (max_entries && count > max_entries) {
printk(KERN_WARNING PREFIX "[%4.4s:0x%02x] ignored %i entries of "
printk(KERN_WARNING PREFIX "[%4.4s:%#x] ignored %i entries of "
"%i found\n", id, entry_id, count - max_entries, count);
}
xen/drivers/acpi/utilities/utglobal.c
+1 -1
View File
@@ -79,7 +79,7 @@ const char *__init acpi_format_exception(acpi_status status)
/* Exception code was not recognized */
ACPI_ERROR((AE_INFO,
"Unknown exception code: 0x%8.8X", status));
"Unknown exception code: %#X", status));
exception = "UNKNOWN_STATUS_CODE";
dump_execution_state();
xen/drivers/cpufreq/cpufreq.c
+1 -1
View File
@@ -377,7 +377,7 @@ static void print_PSS(struct xen_processor_px *ptr, int count)
printk("\t_PSS: state_count=%d\n", count);
for (i=0; i<count; i++){
printk("\tState%d: %"PRId64"MHz %"PRId64"mW %"PRId64"us "
"%"PRId64"us 0x%"PRIx64" 0x%"PRIx64"\n",
"%"PRId64"us %#"PRIx64" %#"PRIx64"\n",
i,
ptr[i].core_frequency,
ptr[i].power,
xen/drivers/passthrough/amd/iommu_acpi.c
+43 -43
View File
@@ -196,7 +196,7 @@ static int __init register_exclusion_range_for_device(
iommu = find_iommu_for_device(seg, bdf);
if ( !iommu )
{
AMD_IOMMU_DEBUG("IVMD Error: No IOMMU for Dev_Id 0x%x!\n", bdf);
AMD_IOMMU_DEBUG("IVMD Error: No IOMMU for Dev_Id %#x!\n", bdf);
return -ENODEV;
}
req = ivrs_mappings[bdf].dte_requestor_id;
@@ -278,7 +278,7 @@ static int __init parse_ivmd_device_select(
bdf = ivmd_block->header.device_id;
if ( bdf >= ivrs_bdf_entries )
{
AMD_IOMMU_DEBUG("IVMD Error: Invalid Dev_Id 0x%x\n", bdf);
AMD_IOMMU_DEBUG("IVMD Error: Invalid Dev_Id %#x\n", bdf);
return -ENODEV;
}
@@ -296,7 +296,7 @@ static int __init parse_ivmd_device_range(
if ( first_bdf >= ivrs_bdf_entries )
{
AMD_IOMMU_DEBUG("IVMD Error: "
"Invalid Range_First Dev_Id 0x%x\n", first_bdf);
"Invalid Range_First Dev_Id %#x\n", first_bdf);
return -ENODEV;
}
@@ -304,7 +304,7 @@ static int __init parse_ivmd_device_range(
if ( (last_bdf >= ivrs_bdf_entries) || (last_bdf <= first_bdf) )
{
AMD_IOMMU_DEBUG("IVMD Error: "
"Invalid Range_Last Dev_Id 0x%x\n", last_bdf);
"Invalid Range_Last Dev_Id %#x\n", last_bdf);
return -ENODEV;
}
@@ -326,7 +326,7 @@ static int __init parse_ivmd_device_iommu(
ivmd_block->aux_data);
if ( !iommu )
{
AMD_IOMMU_DEBUG("IVMD Error: No IOMMU for Dev_Id 0x%x Cap 0x%x\n",
AMD_IOMMU_DEBUG("IVMD Error: No IOMMU for Dev_Id %#x Cap %#x\n",
ivmd_block->header.device_id, ivmd_block->aux_data);
return -ENODEV;
}
@@ -351,9 +351,9 @@ static int __init parse_ivmd_block(const struct acpi_ivrs_memory *ivmd_block)
base = start_addr & PAGE_MASK;
limit = (start_addr + mem_length - 1) & PAGE_MASK;
AMD_IOMMU_DEBUG("IVMD Block: Type 0x%x\n",ivmd_block->header.type);
AMD_IOMMU_DEBUG(" Start_Addr_Phys 0x%lx\n", start_addr);
AMD_IOMMU_DEBUG(" Mem_Length 0x%lx\n", mem_length);
AMD_IOMMU_DEBUG("IVMD Block: Type %#x\n",ivmd_block->header.type);
AMD_IOMMU_DEBUG(" Start_Addr_Phys %#lx\n", start_addr);
AMD_IOMMU_DEBUG(" Mem_Length %#lx\n", mem_length);
if ( ivmd_block->header.flags & ACPI_IVMD_EXCLUSION_RANGE )
iw = ir = IOMMU_CONTROL_ENABLED;
@@ -414,7 +414,7 @@ static u16 __init parse_ivhd_device_select(
bdf = select->header.id;
if ( bdf >= ivrs_bdf_entries )
{
AMD_IOMMU_DEBUG("IVHD Error: Invalid Device_Entry Dev_Id 0x%x\n", bdf);
AMD_IOMMU_DEBUG("IVHD Error: Invalid Device_Entry Dev_Id %#x\n", bdf);
return 0;
}
@@ -439,7 +439,7 @@ static u16 __init parse_ivhd_device_range(
if ( range->end.header.type != ACPI_IVRS_TYPE_END )
{
AMD_IOMMU_DEBUG("IVHD Error: "
"Invalid Range: End_Type 0x%x\n",
"Invalid Range: End_Type %#x\n",
range->end.header.type);
return 0;
}
@@ -448,7 +448,7 @@ static u16 __init parse_ivhd_device_range(
if ( first_bdf >= ivrs_bdf_entries )
{
AMD_IOMMU_DEBUG("IVHD Error: "
"Invalid Range: First Dev_Id 0x%x\n", first_bdf);
"Invalid Range: First Dev_Id %#x\n", first_bdf);
return 0;
}
@@ -456,11 +456,11 @@ static u16 __init parse_ivhd_device_range(
if ( (last_bdf >= ivrs_bdf_entries) || (last_bdf <= first_bdf) )
{
AMD_IOMMU_DEBUG("IVHD Error: "
"Invalid Range: Last Dev_Id 0x%x\n", last_bdf);
"Invalid Range: Last Dev_Id %#x\n", last_bdf);
return 0;
}
AMD_IOMMU_DEBUG(" Dev_Id Range: 0x%x -> 0x%x\n", first_bdf, last_bdf);
AMD_IOMMU_DEBUG(" Dev_Id Range: %#x -> %#x\n", first_bdf, last_bdf);
for ( bdf = first_bdf; bdf <= last_bdf; bdf++ )
add_ivrs_mapping_entry(bdf, bdf, range->start.header.data_setting,
@@ -485,18 +485,18 @@ static u16 __init parse_ivhd_device_alias(
bdf = alias->header.id;
if ( bdf >= ivrs_bdf_entries )
{
AMD_IOMMU_DEBUG("IVHD Error: Invalid Device_Entry Dev_Id 0x%x\n", bdf);
AMD_IOMMU_DEBUG("IVHD Error: Invalid Device_Entry Dev_Id %#x\n", bdf);
return 0;
}
alias_id = alias->used_id;
if ( alias_id >= ivrs_bdf_entries )
{
AMD_IOMMU_DEBUG("IVHD Error: Invalid Alias Dev_Id 0x%x\n", alias_id);
AMD_IOMMU_DEBUG("IVHD Error: Invalid Alias Dev_Id %#x\n", alias_id);
return 0;
}
AMD_IOMMU_DEBUG(" Dev_Id Alias: 0x%x\n", alias_id);
AMD_IOMMU_DEBUG(" Dev_Id Alias: %#x\n", alias_id);
add_ivrs_mapping_entry(bdf, alias_id, alias->header.data_setting, iommu);
@@ -520,7 +520,7 @@ static u16 __init parse_ivhd_device_alias_range(
if ( range->end.header.type != ACPI_IVRS_TYPE_END )
{
AMD_IOMMU_DEBUG("IVHD Error: "
"Invalid Range: End_Type 0x%x\n",
"Invalid Range: End_Type %#x\n",
range->end.header.type);
return 0;
}
@@ -529,7 +529,7 @@ static u16 __init parse_ivhd_device_alias_range(
if ( first_bdf >= ivrs_bdf_entries )
{
AMD_IOMMU_DEBUG("IVHD Error: "
"Invalid Range: First Dev_Id 0x%x\n", first_bdf);
"Invalid Range: First Dev_Id %#x\n", first_bdf);
return 0;
}
@@ -537,19 +537,19 @@ static u16 __init parse_ivhd_device_alias_range(
if ( last_bdf >= ivrs_bdf_entries || last_bdf <= first_bdf )
{
AMD_IOMMU_DEBUG(
"IVHD Error: Invalid Range: Last Dev_Id 0x%x\n", last_bdf);
"IVHD Error: Invalid Range: Last Dev_Id %#x\n", last_bdf);
return 0;
}
alias_id = range->alias.used_id;
if ( alias_id >= ivrs_bdf_entries )
{
AMD_IOMMU_DEBUG("IVHD Error: Invalid Alias Dev_Id 0x%x\n", alias_id);
AMD_IOMMU_DEBUG("IVHD Error: Invalid Alias Dev_Id %#x\n", alias_id);
return 0;
}
AMD_IOMMU_DEBUG(" Dev_Id Range: 0x%x -> 0x%x\n", first_bdf, last_bdf);
AMD_IOMMU_DEBUG(" Dev_Id Alias: 0x%x\n", alias_id);
AMD_IOMMU_DEBUG(" Dev_Id Range: %#x -> %#x\n", first_bdf, last_bdf);
AMD_IOMMU_DEBUG(" Dev_Id Alias: %#x\n", alias_id);
for ( bdf = first_bdf; bdf <= last_bdf; bdf++ )
add_ivrs_mapping_entry(bdf, alias_id, range->alias.header.data_setting,
@@ -574,7 +574,7 @@ static u16 __init parse_ivhd_device_extended(
bdf = ext->header.id;
if ( bdf >= ivrs_bdf_entries )
{
AMD_IOMMU_DEBUG("IVHD Error: Invalid Device_Entry Dev_Id 0x%x\n", bdf);
AMD_IOMMU_DEBUG("IVHD Error: Invalid Device_Entry Dev_Id %#x\n", bdf);
return 0;
}
@@ -599,7 +599,7 @@ static u16 __init parse_ivhd_device_extended_range(
if ( range->end.header.type != ACPI_IVRS_TYPE_END )
{
AMD_IOMMU_DEBUG("IVHD Error: "
"Invalid Range: End_Type 0x%x\n",
"Invalid Range: End_Type %#x\n",
range->end.header.type);
return 0;
}
@@ -608,7 +608,7 @@ static u16 __init parse_ivhd_device_extended_range(
if ( first_bdf >= ivrs_bdf_entries )
{
AMD_IOMMU_DEBUG("IVHD Error: "
"Invalid Range: First Dev_Id 0x%x\n", first_bdf);
"Invalid Range: First Dev_Id %#x\n", first_bdf);
return 0;
}
@@ -616,11 +616,11 @@ static u16 __init parse_ivhd_device_extended_range(
if ( (last_bdf >= ivrs_bdf_entries) || (last_bdf <= first_bdf) )
{
AMD_IOMMU_DEBUG("IVHD Error: "
"Invalid Range: Last Dev_Id 0x%x\n", last_bdf);
"Invalid Range: Last Dev_Id %#x\n", last_bdf);
return 0;
}
AMD_IOMMU_DEBUG(" Dev_Id Range: 0x%x -> 0x%x\n",
AMD_IOMMU_DEBUG(" Dev_Id Range: %#x -> %#x\n",
first_bdf, last_bdf);
for ( bdf = first_bdf; bdf <= last_bdf; bdf++ )
@@ -646,7 +646,7 @@ static u16 __init parse_ivhd_device_special(
bdf = special->used_id;
if ( bdf >= ivrs_bdf_entries )
{
AMD_IOMMU_DEBUG("IVHD Error: Invalid Device_Entry Dev_Id 0x%x\n", bdf);
AMD_IOMMU_DEBUG("IVHD Error: Invalid Device_Entry Dev_Id %#x\n", bdf);
return 0;
}
@@ -673,7 +673,7 @@ static int __init parse_ivhd_block(const struct acpi_ivrs_hardware *ivhd_block)
ivhd_block->capability_offset);
if ( !iommu )
{
AMD_IOMMU_DEBUG("IVHD Error: No IOMMU for Dev_Id 0x%x Cap 0x%x\n",
AMD_IOMMU_DEBUG("IVHD Error: No IOMMU for Dev_Id %#x Cap %#x\n",
ivhd_block->header.device_id,
ivhd_block->capability_offset);
return -ENODEV;
@@ -687,9 +687,9 @@ static int __init parse_ivhd_block(const struct acpi_ivrs_hardware *ivhd_block)
ivhd_device = (const void *)((const u8 *)ivhd_block + block_length);
AMD_IOMMU_DEBUG( "IVHD Device Entry:\n");
AMD_IOMMU_DEBUG( " Type 0x%x\n", ivhd_device->header.type);
AMD_IOMMU_DEBUG( " Dev_Id 0x%x\n", ivhd_device->header.id);
AMD_IOMMU_DEBUG( " Flags 0x%x\n", ivhd_device->header.data_setting);
AMD_IOMMU_DEBUG( " Type %#x\n", ivhd_device->header.type);
AMD_IOMMU_DEBUG( " Dev_Id %#x\n", ivhd_device->header.id);
AMD_IOMMU_DEBUG( " Flags %#x\n", ivhd_device->header.data_setting);
switch ( ivhd_device->header.type )
{
@@ -788,9 +788,9 @@ static void __init dump_acpi_table_header(struct acpi_table_header *table)
printk("%c", table->signature[i]);
printk("\n");
AMD_IOMMU_DEBUG(" Length 0x%x\n", table->length);
AMD_IOMMU_DEBUG(" Revision 0x%x\n", table->revision);
AMD_IOMMU_DEBUG(" CheckSum 0x%x\n", table->checksum);
AMD_IOMMU_DEBUG(" Length %#x\n", table->length);
AMD_IOMMU_DEBUG(" Revision %#x\n", table->revision);
AMD_IOMMU_DEBUG(" CheckSum %#x\n", table->checksum);
AMD_IOMMU_DEBUG(" OEM_Id ");
for ( i = 0; i < ACPI_OEM_ID_SIZE; i++ )
@@ -802,14 +802,14 @@ static void __init dump_acpi_table_header(struct acpi_table_header *table)
printk("%c", table->oem_table_id[i]);
printk("\n");
AMD_IOMMU_DEBUG(" OEM_Revision 0x%x\n", table->oem_revision);
AMD_IOMMU_DEBUG(" OEM_Revision %#x\n", table->oem_revision);
AMD_IOMMU_DEBUG(" Creator_Id ");
for ( i = 0; i < ACPI_NAME_SIZE; i++ )
printk("%c", table->asl_compiler_id[i]);
printk("\n");
AMD_IOMMU_DEBUG(" Creator_Revision 0x%x\n",
AMD_IOMMU_DEBUG(" Creator_Revision %#x\n",
table->asl_compiler_revision);
}
@@ -832,15 +832,15 @@ static int __init parse_ivrs_table(struct acpi_table_header *table)
ivrs_block = (struct acpi_ivrs_header *)((u8 *)table + length);
AMD_IOMMU_DEBUG("IVRS Block:\n");
AMD_IOMMU_DEBUG(" Type 0x%x\n", ivrs_block->type);
AMD_IOMMU_DEBUG(" Flags 0x%x\n", ivrs_block->flags);
AMD_IOMMU_DEBUG(" Length 0x%x\n", ivrs_block->length);
AMD_IOMMU_DEBUG(" Dev_Id 0x%x\n", ivrs_block->device_id);
AMD_IOMMU_DEBUG(" Type %#x\n", ivrs_block->type);
AMD_IOMMU_DEBUG(" Flags %#x\n", ivrs_block->flags);
AMD_IOMMU_DEBUG(" Length %#x\n", ivrs_block->length);
AMD_IOMMU_DEBUG(" Dev_Id %#x\n", ivrs_block->device_id);
if ( table->length < (length + ivrs_block->length) )
{
AMD_IOMMU_DEBUG("IVRS Error: "
"Table Length Exceeded: 0x%x -> 0x%lx\n",
"Table Length Exceeded: %#x -> %#lx\n",
table->length,
(length + ivrs_block->length));
return -ENODEV;
@@ -867,7 +867,7 @@ static int __init detect_iommu_acpi(struct acpi_table_header *table)
checksum += raw_table[i];
if ( checksum )
{
AMD_IOMMU_DEBUG("IVRS Error: Invalid Checksum 0x%x\n", checksum);
AMD_IOMMU_DEBUG("IVRS Error: Invalid Checksum %#x\n", checksum);
return -ENODEV;
}
xen/drivers/passthrough/amd/iommu_init.c
+2 -2
View File
@@ -616,8 +616,8 @@ static void parse_event_log_entry(struct amd_iommu *iommu, u32 entry[])
IOMMU_EVENT_FLAGS_SHIFT);
addr= (u64*) (entry + 2);
printk(XENLOG_ERR "AMD-Vi: "
"%s: domain = %d, device id = 0x%04x, "
"fault address = 0x%"PRIx64", flags = 0x%03x\n",
"%s: domain = %d, device id = %#x, "
"fault address = %#"PRIx64", flags = %#x\n",
event_str[code-1], domain_id, device_id, *addr, flags);
/* Tell the device to stop DMAing; we can't rely on the guest to
xen/drivers/passthrough/amd/iommu_map.c
+1 -1
View File
@@ -795,7 +795,7 @@ void amd_iommu_share_p2m(struct domain *d)
/* When sharing p2m with iommu, paging mode = 4 */
hd->paging_mode = IOMMU_PAGING_MODE_LEVEL_4;
AMD_IOMMU_DEBUG("Share p2m table with iommu: p2m table = 0x%lx\n",
AMD_IOMMU_DEBUG("Share p2m table with iommu: p2m table = %#lx\n",
mfn_x(pgd_mfn));
}
}
xen/drivers/passthrough/amd/pci_amd_iommu.c
+3 -3
View File
@@ -121,8 +121,8 @@ static void amd_iommu_setup_domain_device(
amd_iommu_flush_device(iommu, req_id);
AMD_IOMMU_DEBUG("Setup I/O page table: device id = 0x%04x, "
"root table = 0x%"PRIx64", "
AMD_IOMMU_DEBUG("Setup I/O page table: device id = %#x, "
"root table = %#"PRIx64", "
"domain = %d, paging mode = %d\n", req_id,
page_to_maddr(hd->root_table),
hd->domain_id, hd->paging_mode);
@@ -314,7 +314,7 @@ void amd_iommu_disable_domain_device(struct domain *domain,
amd_iommu_flush_device(iommu, req_id);
AMD_IOMMU_DEBUG("Disable: device id = 0x%04x, "
AMD_IOMMU_DEBUG("Disable: device id = %#x, "
"domain = %d, paging mode = %d\n",
req_id, domain_hvm_iommu(domain)->domain_id,
domain_hvm_iommu(domain)->paging_mode);
xen/drivers/passthrough/vtd/dmar.c
+2 -2
View File
@@ -381,7 +381,7 @@ static int __init acpi_dmar_check_length(
if ( h->length >= min_len )
return 0;
dprintk(XENLOG_ERR VTDPREFIX,
"Invalid ACPI DMAR entry length: 0x%x\n",
"Invalid ACPI DMAR entry length: %#x\n",
h->length);
return -EINVAL;
}
@@ -749,7 +749,7 @@ static int __init acpi_parse_dmar(struct acpi_table_header *table)
break;
default:
dprintk(XENLOG_WARNING VTDPREFIX,
"Ignore unknown DMAR structure type (0x%x)\n",
"Ignore unknown DMAR structure type (%#x)\n",
entry_header->type);
break;
}
xen/drivers/passthrough/vtd/intremap.c
+1 -1
View File
@@ -135,7 +135,7 @@ int iommu_supports_eim(void)
if ( !ioapic_to_drhd(IO_APIC_ID(apic)) )
{
dprintk(XENLOG_WARNING VTDPREFIX,
"There is not a DRHD for IOAPIC 0x%x (id: 0x%x)!\n",
"There is not a DRHD for IOAPIC %#x (id: %#x)!\n",
apic, IO_APIC_ID(apic));
return 0;
}
xen/drivers/passthrough/vtd/iommu.c
+1 -1
View File
@@ -2035,7 +2035,7 @@ static int init_vtd_hw(void)
{
iommu_intremap = 0;
dprintk(XENLOG_ERR VTDPREFIX,
"ioapic_to_iommu: ioapic 0x%x (id: 0x%x) is NULL! "
"ioapic_to_iommu: ioapic %#x (id: %#x) is NULL! "
"Will not try to enable Interrupt Remapping.\n",
apic, IO_APIC_ID(apic));
break;
xen/drivers/passthrough/vtd/utils.c
+1 -1
View File
@@ -217,7 +217,7 @@ static void dump_iommu_info(unsigned char key)
struct iremap_entry *iremap_entries = NULL;
int print_cnt = 0;
printk(" Interrupt remapping table (nr_entry=0x%x. "
printk(" Interrupt remapping table (nr_entry=%#x. "
"Only dump P=1 entries here):\n", nr_entry);
printk(" SVT SQ SID DST V AVL DLM TM RH DM "
"FPD P\n");
xen/drivers/video/vesa.c
+1 -1
View File
@@ -111,7 +111,7 @@ void __init vesa_init(void)
vga_puts = vesa_redraw_puts;
printk(XENLOG_INFO "vesafb: framebuffer at 0x%x, mapped to 0x%p, "
printk(XENLOG_INFO "vesafb: framebuffer at %#x, mapped to 0x%p, "
"using %uk, total %uk\n",
vlfb_info.lfb_base, lfb,
vram_remap >> 10, vram_total >> 10);
Reference in new issue
xen-project/xen
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