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bitkeeper revision 1.1236.1.120 (4241b2ebBzxqlRsKYsrNIy3_dpl_oA)
Remove DOM0_IOPL_PERMISSION since it doesn't make much sense. All admin checks go throu the bitmap mask. Even privileged domains (inc. domain0) must have a mask. Signed-off-by: Keir Fraser <keir@xensource.com>
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5 files changed
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@@ -136,26 +136,6 @@ long arch_do_dom0_op(dom0_op_t *op, dom0_op_t *u_dom0_op)
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}
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break;
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case DOM0_IOPL_PERMISSION:
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{
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struct domain *d;
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ret = -EINVAL;
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if ( op->u.iopl_permission.max_iopl > 3 )
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break;
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ret = -ESRCH;
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if ( unlikely((d = find_domain_by_id(
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op->u.iopl_permission.domain)) == NULL) )
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break;
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ret = 0;
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d->arch.max_iopl = op->u.iopl_permission.max_iopl;
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put_domain(d);
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}
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break;
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case DOM0_IOPORT_PERMISSION:
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{
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struct domain *d;
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@@ -417,9 +417,6 @@ static inline int admin_io_okay(
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struct domain *d = ed->domain;
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u16 x;
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if ( IS_PRIV(d) || (d->arch.max_iopl >= (KERNEL_MODE(ed, regs) ? 1 : 3)) )
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return 1;
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if ( d->arch.iobmp_mask != NULL )
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{
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x = *(u16 *)(d->arch.iobmp_mask + (port >> 3));
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+11
-10
@@ -744,13 +744,17 @@ static int pcidev_dom0_hidden(struct pci_dev *dev)
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/* Domain 0 has read access to all devices. */
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void physdev_init_dom0(struct domain *p)
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void physdev_init_dom0(struct domain *d)
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{
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struct pci_dev *dev;
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phys_dev_t *pdev;
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INFO("Give DOM0 read access to all PCI devices\n");
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/* Access to all I/O ports. */
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d->arch.iobmp_mask = xmalloc_array(u8, IOBMP_BYTES);
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BUG_ON(d->arch.iobmp_mask == NULL);
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memset(d->arch.iobmp_mask, 0, IOBMP_BYTES);
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/* Access to all PCI devices. */
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pci_for_each_dev(dev)
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{
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if ( pcidev_dom0_hidden(dev) )
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@@ -759,20 +763,17 @@ void physdev_init_dom0(struct domain *p)
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continue;
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}
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if ( (pdev = xmalloc(phys_dev_t)) == NULL ) {
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INFO("failed to allocate physical device structure!\n");
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break;
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}
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pdev = xmalloc(phys_dev_t);
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BUG_ON(pdev == NULL);
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pdev->dev = dev;
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pdev->flags = ACC_WRITE;
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pdev->state = 0;
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pdev->owner = p;
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list_add(&pdev->node, &p->pcidev_list);
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pdev->owner = d;
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list_add(&pdev->node, &d->pcidev_list);
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}
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set_bit(DF_PHYSDEV, &p->d_flags);
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set_bit(DF_PHYSDEV, &d->d_flags);
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}
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@@ -20,7 +20,6 @@ struct arch_domain
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/* I/O-port access bitmap mask. */
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u8 *iobmp_mask; /* Address of IO bitmap mask, or NULL. */
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int max_iopl; /* Maximum achievable IOPL. */
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/* shadow mode status and controls */
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unsigned int shadow_mode; /* flags to control shadow table operation */
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@@ -407,13 +407,7 @@ typedef struct {
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u32 _pad0;
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} PACKED dom0_microcode_t; /* 16 bytes */
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#define DOM0_IOPL_PERMISSION 36
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typedef struct {
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domid_t domain; /* 0: domain to be affected */
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u16 max_iopl; /* 2: new effective IOPL limit */
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} PACKED dom0_iopl_permission_t; /* 4 bytes */
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#define DOM0_IOPORT_PERMISSION 37
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#define DOM0_IOPORT_PERMISSION 36
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typedef struct {
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domid_t domain; /* 0: domain to be affected */
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u16 first_port; /* 2: first port int range */
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@@ -455,7 +449,6 @@ typedef struct {
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dom0_read_memtype_t read_memtype;
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dom0_perfccontrol_t perfccontrol;
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dom0_microcode_t microcode;
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dom0_iopl_permission_t iopl_permission;
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dom0_ioport_permission_t ioport_permission;
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} PACKED u;
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} PACKED dom0_op_t; /* 80 bytes */
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