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x86/msr: Shorten ARCH_CAPABILITIES_* constants
They are unnecesserily verbose, and ARCH_CAPS_* is already the more common
version.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
master commit: ba27aaa885
master date: 2019-03-18 16:26:40 +0000
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7ddfc2af15
commit
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2 files changed
+7
-7
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@@ -270,8 +270,8 @@ static void __init print_details(enum ind_thunk thunk, uint64_t caps)
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(_7d0 & cpufeat_mask(X86_FEATURE_L1D_FLUSH)) ? " L1D_FLUSH" : "",
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(_7d0 & cpufeat_mask(X86_FEATURE_SSBD)) ? " SSBD" : "",
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(e8b & cpufeat_mask(X86_FEATURE_IBPB)) ? " IBPB" : "",
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(caps & ARCH_CAPABILITIES_IBRS_ALL) ? " IBRS_ALL" : "",
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(caps & ARCH_CAPABILITIES_RDCL_NO) ? " RDCL_NO" : "",
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(caps & ARCH_CAPS_IBRS_ALL) ? " IBRS_ALL" : "",
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(caps & ARCH_CAPS_RDCL_NO) ? " RDCL_NO" : "",
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(caps & ARCH_CAPS_RSBA) ? " RSBA" : "",
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(caps & ARCH_CAPS_SKIP_L1DFL) ? " SKIP_L1DFL": "",
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(caps & ARCH_CAPS_SSB_NO) ? " SSB_NO" : "");
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@@ -582,7 +582,7 @@ static __init void l1tf_calculations(uint64_t caps)
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}
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/* Any processor advertising RDCL_NO should be not vulnerable to L1TF. */
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if ( caps & ARCH_CAPABILITIES_RDCL_NO )
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if ( caps & ARCH_CAPS_RDCL_NO )
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cpu_has_bug_l1tf = false;
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if ( cpu_has_bug_l1tf && hit_default )
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@@ -646,9 +646,9 @@ int8_t __read_mostly opt_xpti_domu = -1;
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static __init void xpti_init_default(uint64_t caps)
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{
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if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
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caps = ARCH_CAPABILITIES_RDCL_NO;
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caps = ARCH_CAPS_RDCL_NO;
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if ( caps & ARCH_CAPABILITIES_RDCL_NO )
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if ( caps & ARCH_CAPS_RDCL_NO )
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{
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if ( opt_xpti_hwdom < 0 )
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opt_xpti_hwdom = 0;
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@@ -44,8 +44,8 @@
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#define PRED_CMD_IBPB (_AC(1, ULL) << 0)
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#define MSR_ARCH_CAPABILITIES 0x0000010a
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#define ARCH_CAPABILITIES_RDCL_NO (_AC(1, ULL) << 0)
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#define ARCH_CAPABILITIES_IBRS_ALL (_AC(1, ULL) << 1)
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#define ARCH_CAPS_RDCL_NO (_AC(1, ULL) << 0)
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#define ARCH_CAPS_IBRS_ALL (_AC(1, ULL) << 1)
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#define ARCH_CAPS_RSBA (_AC(1, ULL) << 2)
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#define ARCH_CAPS_SKIP_L1DFL (_AC(1, ULL) << 3)
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#define ARCH_CAPS_SSB_NO (_AC(1, ULL) << 4)
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