xen/arm: smmu-v3: Fix MISRA C 2012 Rule 1.3 violations

The expression 1 << 31 produces undefined behaviour because the type of integer
constant 1 is (signed) int and the result of shifting 1 by 31 bits is not
representable in the (signed) int type.
Change the type of 1 to unsigned int by adding the U suffix.

Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com>
Reviewed-by: Rahul Singh <rahul.singh@arm.com>
This commit is contained in:
Xenia Ragiadakou authored and Stefano Stabellini committed 2022-06-28 17:41:27 -07:00
1 parent 8c99264c67
commit 93aa071f66
1 file changed
+2 -2
+2 -2
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@@ -338,7 +338,7 @@ static int platform_get_irq_byname_optional(struct device *dev,
#define CR2_E2H (1 << 0)
#define ARM_SMMU_GBPA 0x44
#define GBPA_UPDATE (1 << 31)
#define GBPA_UPDATE (1U << 31)
#define GBPA_ABORT (1 << 20)
#define ARM_SMMU_IRQ_CTRL 0x50
@@ -410,7 +410,7 @@ static int platform_get_irq_byname_optional(struct device *dev,
#define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1))
#define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift))
#define Q_OVERFLOW_FLAG (1 << 31)
#define Q_OVERFLOW_FLAG (1U << 31)
#define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG)
#define Q_ENT(q, p) ((q)->base + \
Q_IDX(&((q)->llq), p) * \
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