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RISCV/asm: Use CALL rather than JAL
JAL has a maximium displacement of 2M. To branch further, it needs pairing with an AUIPC instruction. CALL is a pseudoinstruction which allows the linker to pick the appropriate sequence when relaxations are enabled. This avoids a build failure of the form: prelink.o: in function `start': xen/xen/arch/riscv/riscv64/head.S:28:(.text.header+0x2c): relocation truncated to fit: R_RISCV_JAL against symbol `calc_phys_offset' defined in .init.text section in prelink.o make[3]: *** [arch/riscv/Makefile:18: xen-syms] Error 1 when Xen gets large enough, e.g. with CONFIG_UBSAN enabled. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
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@@ -49,7 +49,7 @@ save_to_stack:
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REG_S t0, CPU_USER_REGS_SSTATUS(sp)
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mv a0, sp
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jal do_trap
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call do_trap
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restore_registers:
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/* Restore stack_cpu_regs */
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@@ -28,7 +28,7 @@ FUNC(start)
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add t3, t3, __SIZEOF_POINTER__
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bltu t3, t4, .L_clear_bss
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jal reset_stack
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call reset_stack
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/*
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* save hart_id ( bootcpu_id ) and dtb_base as a0 and a1 register can
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@@ -37,16 +37,16 @@ FUNC(start)
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mv s0, a0
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mv s1, a1
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jal calc_phys_offset
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call calc_phys_offset
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mv s2, a0
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jal setup_initial_pagetables
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call setup_initial_pagetables
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/* Calculate proper VA after jump from 1:1 mapping */
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la a0, .L_primary_switched
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sub a0, a0, s2
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jal turn_on_mmu
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call turn_on_mmu
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.L_primary_switched:
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/*
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@@ -54,11 +54,11 @@ FUNC(start)
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* recalculated after jump from 1:1 mapping world as 1:1 mapping
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* will be removed soon in start_xen().
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*/
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jal reset_stack
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call reset_stack
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/* Xen's boot cpu id is equal to 0 so setup TP register for it */
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li a0, 0
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jal setup_tp
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call setup_tp
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/* restore hart_id ( bootcpu_id ) and dtb address */
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mv a0, s0
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