x86/cpuid: Fix Lisbon/Magny-Cours Opterons WRT SSSE3/SSE4A

c/s ff66ccefe5 "x86/CPUID: adjust SSEn dependencies" made SSE4A depend on
SSSE3, but these processors really do have have SSE4A without SSSE3.

This manifests as an upgrade regression, as the SSE4A feature disappears from
view.

Adjust the SSE4A feature to depend on SSE3 rather than SSSE3.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Release-acked-by: Juergen Gross <jgross@suse.com>

xen/tools/gen-cpuid.py

@@ -205,9 +205,10 @@ def crunch_numbers(state):
         # than to SSE.
         SSE2: [SSE3, LM, AESNI, PCLMULQDQ, SHA, GFNI],
 
-        # Other SSEn each depend on their predecessor versions.
-        SSE3: [SSSE3],
-        SSSE3: [SSE4_1, SSE4A],
+        # Other SSEn each depend on their predecessor versions.  AMD
+        # Lisbon/Magny-Cours processors implemented SSE4A without SSSE3.
+        SSE3: [SSSE3, SSE4A],
+        SSSE3: [SSE4_1],
         SSE4_1: [SSE4_2],
 
         # AMD specify no relationship between POPCNT and SSE4.2.  Intel