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x86emul: support AVX-VNNI
These are VEX-encoded equivalents of the EVEX-encoded AVX512-VNNI ISA extension. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Jan Beulich committed
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commit
a780b17c72
9 files changed
+74
-2
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@@ -226,6 +226,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
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{"core-caps", 0x00000007, 0, CPUID_REG_EDX, 30, 1},
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{"ssbd", 0x00000007, 0, CPUID_REG_EDX, 31, 1},
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{"avx-vnni", 0x00000007, 1, CPUID_REG_EAX, 4, 1},
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{"avx512-bf16", 0x00000007, 1, CPUID_REG_EAX, 5, 1},
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{"lahfsahf", 0x80000001, NA, CPUID_REG_ECX, 0, 1},
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@@ -175,7 +175,7 @@ static const char *const str_7d0[32] =
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static const char *const str_7a1[32] =
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{
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/* 4 */ [ 5] = "avx512-bf16",
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[ 4] = "avx-vnni", [ 5] = "avx512-bf16",
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};
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static const struct {
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@@ -1335,6 +1335,10 @@ static const struct vex {
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{ { 0x45 }, 2, T, R, pfx_66, Wn, Ln }, /* vpsrlv{d,q} */
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{ { 0x46 }, 2, T, R, pfx_66, W0, Ln }, /* vpsravd */
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{ { 0x47 }, 2, T, R, pfx_66, Wn, Ln }, /* vpsllv{d,q} */
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{ { 0x50 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusd */
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{ { 0x51 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusds */
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{ { 0x52 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwssd */
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{ { 0x53 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwssds */
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{ { 0x58 }, 2, T, R, pfx_66, W0, Ln }, /* vpbroadcastd */
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{ { 0x59 }, 2, T, R, pfx_66, W0, Ln }, /* vpbroadcastq */
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{ { 0x5a }, 2, F, R, pfx_66, W0, L1 }, /* vbroadcasti128 */
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@@ -5028,6 +5028,61 @@ int main(int argc, char **argv)
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printf("okay\n");
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}
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printf("%-40s", "Testing vpdpwssd (%ecx),%{y,z}mmA,%{y,z}mmB...");
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if ( stack_exec && cpu_has_avx512_vnni && cpu_has_avx_vnni )
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{
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/* Do the same operation two ways and compare the results. */
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decl_insn(vpdpwssd_vex1);
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decl_insn(vpdpwssd_vex2);
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decl_insn(vpdpwssd_evex);
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for ( i = 0; i < 24; ++i )
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res[i] = i | (~i << 16);
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asm volatile ( "vmovdqu32 32(%0), %%zmm1\n\t"
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"vextracti64x4 $1, %%zmm1, %%ymm2\n\t"
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"vpxor %%xmm0, %%xmm0, %%xmm3\n\t"
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"vpxor %%xmm0, %%xmm0, %%xmm4\n\t"
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"vpxor %%xmm0, %%xmm0, %%xmm5\n"
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put_insn(vpdpwssd_vex1,
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/* %{vex%} vpdpwssd (%1), %%ymm1, %%ymm3" */
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".byte 0xc4, 0xe2, 0x75, 0x52, 0x19") "\n"
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put_insn(vpdpwssd_vex2,
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/* "%{vex%} vpdpwssd 32(%1), %%ymm2, %%ymm4" */
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".byte 0xc4, 0xe2, 0x6d, 0x52, 0x61, 0x20") "\n"
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put_insn(vpdpwssd_evex,
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/* "vpdpwssd (%1), %%zmm1, %%zmm5" */
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".byte 0x62, 0xf2, 0x75, 0x48, 0x52, 0x29")
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:: "r" (res), "c" (NULL) );
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set_insn(vpdpwssd_vex1);
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regs.ecx = (unsigned long)res;
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rc = x86_emulate(&ctxt, &emulops);
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if ( rc != X86EMUL_OKAY || !check_eip(vpdpwssd_vex1) )
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goto fail;
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set_insn(vpdpwssd_vex2);
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regs.ecx = (unsigned long)res;
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rc = x86_emulate(&ctxt, &emulops);
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if ( rc != X86EMUL_OKAY || !check_eip(vpdpwssd_vex2) )
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goto fail;
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set_insn(vpdpwssd_evex);
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regs.ecx = (unsigned long)res;
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rc = x86_emulate(&ctxt, &emulops);
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if ( rc != X86EMUL_OKAY || !check_eip(vpdpwssd_evex) )
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goto fail;
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asm ( "vinserti64x4 $1, %%ymm4, %%zmm3, %%zmm0\n\t"
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"vpcmpeqd %%zmm0, %%zmm5, %%k0\n\t"
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"kmovw %%k0, %0" : "=g" (rc) );
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if ( rc != 0xffff )
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goto fail;
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printf("okay\n");
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}
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else
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printf("skipped\n");
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printf("%-40s", "Testing invpcid 16(%ecx),%%edx...");
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if ( stack_exec )
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{
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@@ -170,6 +170,7 @@ static inline bool xcr0_mask(uint64_t mask)
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#define cpu_has_avx512_4fmaps (cp.feat.avx512_4fmaps && xcr0_mask(0xe6))
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#define cpu_has_avx512_vp2intersect (cp.feat.avx512_vp2intersect && xcr0_mask(0xe6))
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#define cpu_has_serialize cp.feat.serialize
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#define cpu_has_avx_vnni (cp.feat.avx_vnni && xcr0_mask(6))
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#define cpu_has_avx512_bf16 (cp.feat.avx512_bf16 && xcr0_mask(0xe6))
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#define cpu_has_xgetbv1 (cpu_has_xsave && cp.xstate.xgetbv1)
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@@ -2008,6 +2008,7 @@ amd_like(const struct x86_emulate_ctxt *ctxt)
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#define vcpu_has_avx512_4fmaps() (ctxt->cpuid->feat.avx512_4fmaps)
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#define vcpu_has_avx512_vp2intersect() (ctxt->cpuid->feat.avx512_vp2intersect)
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#define vcpu_has_serialize() (ctxt->cpuid->feat.serialize)
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#define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni)
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#define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16)
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#define vcpu_must_have(feat) \
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@@ -9453,6 +9454,14 @@ x86_emulate(
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generate_exception_if(vex.l, EXC_UD);
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goto simd_0f_avx;
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case X86EMUL_OPC_VEX_66(0x0f38, 0x50): /* vpdpbusd [xy]mm/mem,[xy]mm,[xy]mm */
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case X86EMUL_OPC_VEX_66(0x0f38, 0x51): /* vpdpbusds [xy]mm/mem,[xy]mm,[xy]mm */
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case X86EMUL_OPC_VEX_66(0x0f38, 0x52): /* vpdpwssd [xy]mm/mem,[xy]mm,[xy]mm */
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case X86EMUL_OPC_VEX_66(0x0f38, 0x53): /* vpdpwssds [xy]mm/mem,[xy]mm,[xy]mm */
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host_and_vcpu_must_have(avx_vnni);
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generate_exception_if(vex.w, EXC_UD);
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goto simd_0f_avx;
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case X86EMUL_OPC_EVEX_66(0x0f38, 0x50): /* vpdpbusd [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
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case X86EMUL_OPC_EVEX_66(0x0f38, 0x51): /* vpdpbusds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
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case X86EMUL_OPC_EVEX_66(0x0f38, 0x52): /* vpdpwssd [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
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@@ -133,6 +133,7 @@
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#define cpu_has_serialize boot_cpu_has(X86_FEATURE_SERIALIZE)
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/* CPUID level 0x00000007:1.eax */
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#define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI)
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#define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16)
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/* Synthesized. */
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@@ -273,6 +273,7 @@ XEN_CPUFEATURE(CORE_CAPS, 9*32+30) /* IA32_CORE_CAPABILITIES MSR */
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XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */
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/* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */
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XEN_CPUFEATURE(AVX_VNNI, 10*32+ 4) /*A AVX-VNNI Instructions */
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XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */
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#endif /* XEN_CPUFEATURE */
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@@ -252,7 +252,7 @@ def crunch_numbers(state):
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# feature flags. If want to use AVX512, AVX2 must be supported and
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# enabled. Certain later extensions, acting on 256-bit vectors of
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# integers, better depend on AVX2 than AVX.
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AVX2: [AVX512F, VAES, VPCLMULQDQ],
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AVX2: [AVX512F, VAES, VPCLMULQDQ, AVX_VNNI],
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# AVX512F is taken to mean hardware support for 512bit registers
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# (which in practice depends on the EVEX prefix to encode) as well
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