x86/compat: Cleanup and further debugging of SMAP/SMEP fixup

* Abstract (X86_CR4_SMEP | X86_CR4_SMAP) behind XEN_CR4_PV32_BITS to avoid
   opencoding the invidial bits which are fixed up behind a 32bit PV guests
   back.
 * In the debug case, perform the the AND and CMP on 64bit values rather than
   32bit values, to match the logic in then non-debug case.
 * Show cr4_pv32_mask in the BUG register dump

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
Release-acked-by: Wei Liu <wei.liu2@citrix.com>
This commit is contained in:
Andrew Cooper committed 2016-05-16 13:11:05 +01:00
1 parent fcab4cec98
commit ad4aa3619f
3 files changed
+8 -4

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+1 -1
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@@ -1400,7 +1400,7 @@ void __init noreturn __start_xen(unsigned long mbi_p)
if ( cpu_has_smap )
set_in_cr4(X86_CR4_SMAP);
cr4_pv32_mask = mmu_cr4_features & (X86_CR4_SMEP | X86_CR4_SMAP);
cr4_pv32_mask = mmu_cr4_features & XEN_CR4_PV32_BITS;
if ( cpu_has_fsgsbase )
set_in_cr4(X86_CR4_FSGSBASE);
+5 -3
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@@ -204,7 +204,7 @@ ENTRY(cr4_pv32_restore)
push %rdx
GET_CPUINFO_FIELD(cr4, dx)
mov (%rdx), %rax
test $X86_CR4_SMEP|X86_CR4_SMAP,%eax
test $XEN_CR4_PV32_BITS, %eax
jnz 0f
or cr4_pv32_mask(%rip), %rax
mov %rax, %cr4
@@ -215,9 +215,11 @@ ENTRY(cr4_pv32_restore)
#ifndef NDEBUG
/* Check that _all_ of the bits intended to be set actually are. */
mov %cr4, %rax
and cr4_pv32_mask(%rip), %eax
cmp cr4_pv32_mask(%rip), %eax
and cr4_pv32_mask(%rip), %rax
cmp cr4_pv32_mask(%rip), %rax
je 1f
/* Cause cr4_pv32_mask to be visible in the BUG register dump. */
mov cr4_pv32_mask(%rip), %rdx
BUG
1:
#endif
+2
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@@ -151,6 +151,8 @@
#define XEN_MINIMAL_CR4 (X86_CR4_PGE | X86_CR4_PAE)
#define XEN_CR4_PV32_BITS (X86_CR4_SMEP|X86_CR4_SMAP)
#define XEN_SYSCALL_MASK (X86_EFLAGS_AC|X86_EFLAGS_VM|X86_EFLAGS_RF| \
X86_EFLAGS_NT|X86_EFLAGS_DF|X86_EFLAGS_IF| \
X86_EFLAGS_TF)
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