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x86/compat: Cleanup and further debugging of SMAP/SMEP fixup
* Abstract (X86_CR4_SMEP | X86_CR4_SMAP) behind XEN_CR4_PV32_BITS to avoid opencoding the invidial bits which are fixed up behind a 32bit PV guests back. * In the debug case, perform the the AND and CMP on 64bit values rather than 32bit values, to match the logic in then non-debug case. * Show cr4_pv32_mask in the BUG register dump Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Wei Liu <wei.liu2@citrix.com> Release-acked-by: Wei Liu <wei.liu2@citrix.com>
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@@ -1400,7 +1400,7 @@ void __init noreturn __start_xen(unsigned long mbi_p)
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if ( cpu_has_smap )
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set_in_cr4(X86_CR4_SMAP);
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cr4_pv32_mask = mmu_cr4_features & (X86_CR4_SMEP | X86_CR4_SMAP);
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cr4_pv32_mask = mmu_cr4_features & XEN_CR4_PV32_BITS;
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if ( cpu_has_fsgsbase )
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set_in_cr4(X86_CR4_FSGSBASE);
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@@ -204,7 +204,7 @@ ENTRY(cr4_pv32_restore)
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push %rdx
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GET_CPUINFO_FIELD(cr4, dx)
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mov (%rdx), %rax
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test $X86_CR4_SMEP|X86_CR4_SMAP,%eax
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test $XEN_CR4_PV32_BITS, %eax
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jnz 0f
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or cr4_pv32_mask(%rip), %rax
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mov %rax, %cr4
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@@ -215,9 +215,11 @@ ENTRY(cr4_pv32_restore)
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#ifndef NDEBUG
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/* Check that _all_ of the bits intended to be set actually are. */
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mov %cr4, %rax
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and cr4_pv32_mask(%rip), %eax
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cmp cr4_pv32_mask(%rip), %eax
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and cr4_pv32_mask(%rip), %rax
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cmp cr4_pv32_mask(%rip), %rax
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je 1f
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/* Cause cr4_pv32_mask to be visible in the BUG register dump. */
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mov cr4_pv32_mask(%rip), %rdx
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BUG
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1:
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#endif
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@@ -151,6 +151,8 @@
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#define XEN_MINIMAL_CR4 (X86_CR4_PGE | X86_CR4_PAE)
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#define XEN_CR4_PV32_BITS (X86_CR4_SMEP|X86_CR4_SMAP)
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#define XEN_SYSCALL_MASK (X86_EFLAGS_AC|X86_EFLAGS_VM|X86_EFLAGS_RF| \
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X86_EFLAGS_NT|X86_EFLAGS_DF|X86_EFLAGS_IF| \
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X86_EFLAGS_TF)
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