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x86/hvm: Fix Misra Rule 19.1 regression
Despite noticing an impending Rule 19.1 violation, the adjustment made (the uint32_t cast) wasn't sufficient to avoid it. Try again. Subsequently noticed by Coverity too. Fixes:6a98383b08("x86/HVM: clear upper halves of GPRs upon entry from 32-bit code") Coverity-IDs: 1596289 thru 1596298 Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> master commit:d0a718a45fmaster date: 2024-04-11 13:23:08 +0100
This commit is contained in:
Andrew Cooper authored and 
Jan Beulich committed
1 parent
2044364864
commit
ae19cd743c
1 file changed
+10
-10
@@ -589,16 +589,16 @@ static inline void hvm_sanitize_regs_fields(struct cpu_user_regs *regs,
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if ( compat )
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{
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/* Clear GPR upper halves, to counteract guests playing games. */
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regs->rbp = (uint32_t)regs->ebp;
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regs->rbx = (uint32_t)regs->ebx;
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regs->rax = (uint32_t)regs->eax;
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regs->rcx = (uint32_t)regs->ecx;
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regs->rdx = (uint32_t)regs->edx;
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regs->rsi = (uint32_t)regs->esi;
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regs->rdi = (uint32_t)regs->edi;
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regs->rip = (uint32_t)regs->eip;
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regs->rflags = (uint32_t)regs->eflags;
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regs->rsp = (uint32_t)regs->esp;
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regs->rbp = (uint32_t)regs->rbp;
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regs->rbx = (uint32_t)regs->rbx;
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regs->rax = (uint32_t)regs->rax;
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regs->rcx = (uint32_t)regs->rcx;
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regs->rdx = (uint32_t)regs->rdx;
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regs->rsi = (uint32_t)regs->rsi;
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regs->rdi = (uint32_t)regs->rdi;
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regs->rip = (uint32_t)regs->rip;
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regs->rflags = (uint32_t)regs->rflags;
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regs->rsp = (uint32_t)regs->rsp;
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}
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#ifndef NDEBUG
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