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xen/arm: smmuv3: Remove the page 1 fixup
Backport Linux commit 86d2d9214880. This is the clean backport without
any changes.
Since we now keep track of page 1 via a separate pointer that
already encapsulates aliasing to page 0 as necessary, we can remove
the clunky fixup routine and simply use the relevant bases directly.
The current architecture spec (IHI0070D.a) defines
SMMU_{EVENTQ,PRIQ}_{PROD,CONS} as offsets relative to page 1, so the
cleanup represents a little bit of convergence as well as just
lines of code saved.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 86d2d9214880
Signed-off-by: Rahul Singh <rahul.singh@arm.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>
This commit is contained in:
Robin Murphy authored and 
Julien Grall committed
1 parent
19f609249a
commit
ae4ee09eb3
2 files changed
+20
-30
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@@ -238,15 +238,6 @@ static struct arm_smmu_option_prop arm_smmu_options[] = {
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{ 0, NULL},
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};
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static inline void __iomem *arm_smmu_page1_fixup(unsigned long offset,
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struct arm_smmu_device *smmu)
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{
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if (offset > SZ_64K)
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return smmu->page1 + offset - SZ_64K;
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return smmu->base + offset;
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}
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static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
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{
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return container_of(dom, struct arm_smmu_domain, domain);
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@@ -1581,6 +1572,7 @@ static int arm_smmu_dt_xlate(struct device *dev,
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/* Probing and initialisation functions */
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static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
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struct arm_smmu_queue *q,
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void __iomem *page,
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unsigned long prod_off,
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unsigned long cons_off,
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size_t dwords, const char *name)
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@@ -1609,8 +1601,8 @@ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
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1 << q->llq.max_n_shift, name);
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}
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q->prod_reg = arm_smmu_page1_fixup(prod_off, smmu);
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q->cons_reg = arm_smmu_page1_fixup(cons_off, smmu);
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q->prod_reg = page + prod_off;
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q->cons_reg = page + cons_off;
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q->ent_dwords = dwords;
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q->q_base = Q_BASE_RWA;
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@@ -1627,16 +1619,16 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu)
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/* cmdq */
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spin_lock_init(&smmu->cmdq.lock);
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ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, ARM_SMMU_CMDQ_PROD,
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ARM_SMMU_CMDQ_CONS, CMDQ_ENT_DWORDS,
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"cmdq");
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ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base,
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ARM_SMMU_CMDQ_PROD, ARM_SMMU_CMDQ_CONS,
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CMDQ_ENT_DWORDS, "cmdq");
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if (ret)
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return ret;
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/* evtq */
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ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, ARM_SMMU_EVTQ_PROD,
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ARM_SMMU_EVTQ_CONS, EVTQ_ENT_DWORDS,
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"evtq");
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ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1,
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ARM_SMMU_EVTQ_PROD, ARM_SMMU_EVTQ_CONS,
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EVTQ_ENT_DWORDS, "evtq");
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if (ret)
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return ret;
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@@ -1644,9 +1636,9 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu)
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if (!(smmu->features & ARM_SMMU_FEAT_PRI))
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return 0;
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return arm_smmu_init_one_queue(smmu, &smmu->priq.q, ARM_SMMU_PRIQ_PROD,
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ARM_SMMU_PRIQ_CONS, PRIQ_ENT_DWORDS,
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"priq");
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return arm_smmu_init_one_queue(smmu, &smmu->priq.q, smmu->page1,
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ARM_SMMU_PRIQ_PROD, ARM_SMMU_PRIQ_CONS,
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PRIQ_ENT_DWORDS, "priq");
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}
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static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu)
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@@ -2090,10 +2082,8 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
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/* Event queue */
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writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE);
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writel_relaxed(smmu->evtq.q.llq.prod,
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arm_smmu_page1_fixup(ARM_SMMU_EVTQ_PROD, smmu));
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writel_relaxed(smmu->evtq.q.llq.cons,
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arm_smmu_page1_fixup(ARM_SMMU_EVTQ_CONS, smmu));
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writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD);
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writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS);
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enables |= CR0_EVTQEN;
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ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
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@@ -2108,9 +2098,9 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
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writeq_relaxed(smmu->priq.q.q_base,
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smmu->base + ARM_SMMU_PRIQ_BASE);
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writel_relaxed(smmu->priq.q.llq.prod,
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arm_smmu_page1_fixup(ARM_SMMU_PRIQ_PROD, smmu));
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smmu->page1 + ARM_SMMU_PRIQ_PROD);
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writel_relaxed(smmu->priq.q.llq.cons,
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arm_smmu_page1_fixup(ARM_SMMU_PRIQ_CONS, smmu));
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smmu->page1 + ARM_SMMU_PRIQ_CONS);
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enables |= CR0_PRIQEN;
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ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
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@@ -130,15 +130,15 @@
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#define ARM_SMMU_CMDQ_CONS 0x9c
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#define ARM_SMMU_EVTQ_BASE 0xa0
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#define ARM_SMMU_EVTQ_PROD 0x100a8
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#define ARM_SMMU_EVTQ_CONS 0x100ac
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#define ARM_SMMU_EVTQ_PROD 0xa8
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#define ARM_SMMU_EVTQ_CONS 0xac
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#define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0
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#define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8
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#define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc
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#define ARM_SMMU_PRIQ_BASE 0xc0
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#define ARM_SMMU_PRIQ_PROD 0x100c8
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#define ARM_SMMU_PRIQ_CONS 0x100cc
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#define ARM_SMMU_PRIQ_PROD 0xc8
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#define ARM_SMMU_PRIQ_CONS 0xcc
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#define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0
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#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8
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#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc
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