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hvmloader: Assign PCI resources in descending order of size for better packing.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
This commit is contained in:
Keir Fraser committed
1 parent
d81a1d35a9
commit
b126cbcb88
1 file changed
+61
-29
@@ -188,6 +188,12 @@ static void pci_setup(void)
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uint16_t class, vendor_id, device_id;
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unsigned int bar, pin, link, isa_irq;
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/* Create a list of device BARs in descending order of size. */
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struct bars {
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uint32_t devfn, bar_reg, bar_sz;
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} *bars = (struct bars *)0xc0000;
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unsigned int i, nr_bars = 0;
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/* Program PCI-ISA bridge with appropriate link routes. */
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isa_irq = 0;
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for ( link = 0; link < 4; link++ )
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@@ -242,44 +248,30 @@ static void pci_setup(void)
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bar_reg = PCI_ROM_ADDRESS;
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bar_data = pci_readl(devfn, bar_reg);
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pci_writel(devfn, bar_reg, ~0);
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bar_sz = pci_readl(devfn, bar_reg);
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pci_writel(devfn, bar_reg, bar_data);
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if ( bar_sz == 0 )
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continue;
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if ( (bar_data & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY )
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{
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base = &mem_base;
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bar_sz &= PCI_BASE_ADDRESS_MEM_MASK;
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bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK;
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}
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else
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{
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base = &io_base;
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bar_sz &= PCI_BASE_ADDRESS_IO_MASK & 0xffff;
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bar_data &= ~PCI_BASE_ADDRESS_IO_MASK;
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}
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bar_sz &= (((bar_data & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY) ?
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PCI_BASE_ADDRESS_MEM_MASK :
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(PCI_BASE_ADDRESS_IO_MASK & 0xffff));
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bar_sz &= ~(bar_sz - 1);
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*base = (*base + bar_sz - 1) & ~(bar_sz - 1);
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bar_data |= *base;
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*base += bar_sz;
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for ( i = 0; i < nr_bars; i++ )
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if ( bars[i].bar_sz < bar_sz )
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break;
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pci_writel(devfn, bar_reg, bar_data);
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printf("pci dev %02x:%x bar %02x size %08x: %08x\n",
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devfn>>3, devfn&7, bar_reg, bar_sz, bar_data);
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if ( i != nr_bars )
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memmove(&bars[i+1], &bars[i], (nr_bars-i) * sizeof(*bars));
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/* Now enable the memory or I/O mapping. */
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cmd = pci_readw(devfn, PCI_COMMAND);
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if ( (bar_reg == PCI_ROM_ADDRESS) ||
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((bar_data & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY) )
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cmd |= PCI_COMMAND_MEMORY;
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else
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cmd |= PCI_COMMAND_IO;
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pci_writew(devfn, PCI_COMMAND, cmd);
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bars[i].devfn = devfn;
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bars[i].bar_reg = bar_reg;
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bars[i].bar_sz = bar_sz;
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nr_bars++;
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}
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break;
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}
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@@ -296,6 +288,46 @@ static void pci_setup(void)
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devfn>>3, devfn&7, 'A'+pin-1, isa_irq);
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}
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}
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/* Assign iomem and ioport resources in descending order of size. */
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for ( i = 0; i < nr_bars; i++ )
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{
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devfn = bars[i].devfn;
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bar_reg = bars[i].bar_reg;
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bar_sz = bars[i].bar_sz;
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bar_data = pci_readl(devfn, bar_reg);
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if ( (bar_data & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY )
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{
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base = &mem_base;
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bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK;
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}
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else
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{
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base = &io_base;
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bar_data &= ~PCI_BASE_ADDRESS_IO_MASK;
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}
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*base = (*base + bar_sz - 1) & ~(bar_sz - 1);
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bar_data |= *base;
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*base += bar_sz;
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pci_writel(devfn, bar_reg, bar_data);
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printf("pci dev %02x:%x bar %02x size %08x: %08x %08x/%08x\n",
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devfn>>3, devfn&7, bar_reg, bar_sz, bar_data, i, nr_bars);
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/* Now enable the memory or I/O mapping. */
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cmd = pci_readw(devfn, PCI_COMMAND);
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if ( (bar_reg == PCI_ROM_ADDRESS) ||
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((bar_data & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY) )
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cmd |= PCI_COMMAND_MEMORY;
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else
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cmd |= PCI_COMMAND_IO;
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pci_writew(devfn, PCI_COMMAND, cmd);
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}
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}
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/*
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