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x86/spec-ctrl: CPUID/MSR definitions for Microarchitectural Data Sampling

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The MD_CLEAR feature can be automatically offered to guests.  No
infrastructure is needed in Xen to support the guest making use of it.

This is part of XSA-297, CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
(cherry picked from commit d4f6116c08)
This commit is contained in:
Andrew Cooper committed 2019-05-14 15:40:19 +01:00
1 parent 0771bb653d
commit b32dde342c
7 files changed
+20 -7
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docs/misc/xen-command-line.markdown
+1 -1
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@@ -496,7 +496,7 @@ accounting for hardware capabilities as enumerated via CPUID.
Currently accepted:
The Speculation Control hardware features `ibrsb`, `stibp`, `ibpb`,
The Speculation Control hardware features `md-clear`, `ibrsb`, `stibp`, `ibpb`,
`l1d-flush` and `ssbd` are used by default if available and applicable. They can
be ignored, e.g. `no-ibrsb`, at which point Xen won't use them itself, and
won't offer them to guests.
tools/libxl/libxl_cpuid.c
+1
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@@ -202,6 +202,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
{"avx512-4vnniw",0x00000007, 0, CPUID_REG_EDX, 2, 1},
{"avx512-4fmaps",0x00000007, 0, CPUID_REG_EDX, 3, 1},
{"md-clear", 0x00000007, 0, CPUID_REG_EDX, 10, 1},
{"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1},
{"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1},
{"l1d-flush", 0x00000007, 0, CPUID_REG_EDX, 28, 1},
tools/misc/xen-cpuid.c
+2 -1
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@@ -162,8 +162,9 @@ static const char *str_7d0[32] =
[ 2] = "avx512_4vnniw", [ 3] = "avx512_4fmaps",
[4 ... 11] = "REZ",
[4 ... 9] = "REZ",
[10] = "md-clear", [11] = "REZ",
[12] = "REZ", [13] = "tsx-force-abort",
[14 ... 25] = "REZ",
xen/arch/x86/cpuid.c
+6 -1
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@@ -28,7 +28,12 @@ static int __init parse_xen_cpuid(const char *s)
if ( !ss )
ss = strchr(s, '\0');
if ( (val = parse_boolean("ibpb", s, ss)) >= 0 )
if ( (val = parse_boolean("md-clear", s, ss)) >= 0 )
{
if ( !val )
setup_clear_cpu_cap(X86_FEATURE_MD_CLEAR);
}
else if ( (val = parse_boolean("ibpb", s, ss)) >= 0 )
{
if ( !val )
setup_clear_cpu_cap(X86_FEATURE_IBPB);
xen/arch/x86/spec_ctrl.c
+8 -4
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@@ -331,17 +331,19 @@ static void __init print_details(enum ind_thunk thunk, uint64_t caps)
printk("Speculative mitigation facilities:\n");
/* Hardware features which pertain to speculative mitigations. */
printk(" Hardware features:%s%s%s%s%s%s%s%s%s%s\n",
printk(" Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s\n",
(_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBRS/IBPB" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_L1D_FLUSH)) ? " L1D_FLUSH" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_SSBD)) ? " SSBD" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_MD_CLEAR)) ? " MD_CLEAR" : "",
(e8b & cpufeat_mask(X86_FEATURE_IBPB)) ? " IBPB" : "",
(caps & ARCH_CAPS_IBRS_ALL) ? " IBRS_ALL" : "",
(caps & ARCH_CAPS_RDCL_NO) ? " RDCL_NO" : "",
(caps & ARCH_CAPS_RSBA) ? " RSBA" : "",
(caps & ARCH_CAPS_SKIP_L1DFL) ? " SKIP_L1DFL": "",
(caps & ARCH_CAPS_SSB_NO) ? " SSB_NO" : "");
(caps & ARCH_CAPS_SSB_NO) ? " SSB_NO" : "",
(caps & ARCH_CAPS_MDS_NO) ? " MDS_NO" : "");
/* Compiled-in support which pertains to mitigations. */
if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) || IS_ENABLED(CONFIG_SHADOW_PAGING) )
@@ -378,19 +380,21 @@ static void __init print_details(enum ind_thunk thunk, uint64_t caps)
* Alternatives blocks for protecting against and/or virtualising
* mitigation support for guests.
*/
printk(" Support for VMs: PV:%s%s%s%s, HVM:%s%s%s%s\n",
printk(" Support for VMs: PV:%s%s%s%s%s, HVM:%s%s%s%s%s\n",
(boot_cpu_has(X86_FEATURE_SC_MSR_PV) ||
boot_cpu_has(X86_FEATURE_SC_RSB_PV) ||
opt_eager_fpu) ? "" : " None",
boot_cpu_has(X86_FEATURE_SC_MSR_PV) ? " MSR_SPEC_CTRL" : "",
boot_cpu_has(X86_FEATURE_SC_RSB_PV) ? " RSB" : "",
opt_eager_fpu ? " EAGER_FPU" : "",
boot_cpu_has(X86_FEATURE_MD_CLEAR) ? " MD_CLEAR" : "",
(boot_cpu_has(X86_FEATURE_SC_MSR_HVM) ||
boot_cpu_has(X86_FEATURE_SC_RSB_HVM) ||
opt_eager_fpu) ? "" : " None",
boot_cpu_has(X86_FEATURE_SC_MSR_HVM) ? " MSR_SPEC_CTRL" : "",
boot_cpu_has(X86_FEATURE_SC_RSB_HVM) ? " RSB" : "",
opt_eager_fpu ? " EAGER_FPU" : "");
opt_eager_fpu ? " EAGER_FPU" : "",
boot_cpu_has(X86_FEATURE_MD_CLEAR) ? " MD_CLEAR" : "");
printk(" XPTI (64-bit PV only): Dom0 %s, DomU %s\n",
opt_xpti_hwdom ? "enabled" : "disabled",
xen/include/asm-x86/msr-index.h
+1
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@@ -53,6 +53,7 @@
#define ARCH_CAPS_RSBA (_AC(1, ULL) << 2)
#define ARCH_CAPS_SKIP_L1DFL (_AC(1, ULL) << 3)
#define ARCH_CAPS_SSB_NO (_AC(1, ULL) << 4)
#define ARCH_CAPS_MDS_NO (_AC(1, ULL) << 5)
#define MSR_FLUSH_CMD 0x0000010b
#define FLUSH_CMD_L1D (_AC(1, ULL) << 0)
xen/include/public/arch-x86/cpufeatureset.h
+1
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@@ -242,6 +242,7 @@ XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by
/* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */
XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */
XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*A VERW clears microarchitectural buffers */
XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */
XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */
XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */
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