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x86/msr: Use the architectural layout for MSR_{MISC_ENABLES,PLATFORM_INFO}
This simplifies future interactions with the toolstack, by removing the need for per-MSR custom accessors when shuffling data in/out of a policy. Use a 32bit raw backing integer (for simplicity), and use a bitfield to move the cpuid_faulting field to its appropriate position. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Sergey Dyasli <sergey.dyasli@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com>
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@@ -139,8 +139,7 @@ int guest_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
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break;
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case MSR_INTEL_PLATFORM_INFO:
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*val = (uint64_t)dp->plaform_info.cpuid_faulting <<
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_MSR_PLATFORM_INFO_CPUID_FAULTING;
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*val = dp->plaform_info.raw;
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break;
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case MSR_ARCH_CAPABILITIES:
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@@ -148,8 +147,7 @@ int guest_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
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goto gp_fault;
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case MSR_INTEL_MISC_FEATURES_ENABLES:
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*val = (uint64_t)vp->misc_features_enables.cpuid_faulting <<
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_MSR_MISC_FEATURES_CPUID_FAULTING;
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*val = vp->misc_features_enables.raw;
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break;
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default:
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@@ -240,8 +238,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
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if ( val & rsvd )
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goto gp_fault;
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vp->misc_features_enables.cpuid_faulting =
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val & MSR_MISC_FEATURES_CPUID_FAULTING;
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vp->misc_features_enables.raw = val;
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if ( v == curr && is_hvm_domain(d) && cpu_has_cpuid_faulting &&
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(old_cpuid_faulting ^ vp->misc_features_enables.cpuid_faulting) )
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@@ -268,8 +268,12 @@ struct msr_domain_policy
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* guests so can be offered unconditionally, while support for PV guests
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* is dependent on real hardware support.
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*/
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struct {
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bool cpuid_faulting;
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union {
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uint32_t raw;
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struct {
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uint32_t :31;
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bool cpuid_faulting:1;
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};
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} plaform_info;
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};
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@@ -301,8 +305,11 @@ struct msr_vcpu_policy
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* unconditionally. The CPUID Faulting bit is the only writeable bit, and
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* only if enumerated by MSR_PLATFORM_INFO.
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*/
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struct {
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bool cpuid_faulting;
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union {
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uint32_t raw;
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struct {
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bool cpuid_faulting:1;
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};
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} misc_features_enables;
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};
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